Probe Buffering Unit for Selective Cache Coherency Probe Filtering
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Solution Overview
Problem
Current processor implementations are inefficient in handling cache coherency probes, particularly invalidation probes, leading to resource wastage in terms of time, power, and hardware resources due to overinclusive actions or excessive evaluation, which can cause slowdowns and throughput degradation.
Innovation Solution
A processor with a probe buffering unit that selectively filters, buffers, and processes cache coherency probes using a microtag comparator to distinguish between cached and non-cached memory blocks, prioritizing current memory access requests over invalidation probes and applying buffered invalidation probes only when necessary, thereby reducing unnecessary actions and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If every invalidation probe is fully evaluated before taking responsive actions, then the accuracy of probe handling is improved, but the processing time and throughput are degraded
Solution Approach 1:
The patent applies partial action by implementing a two-stage probe evaluation process. First, a quick filter check determines if the probe target address falls within the cached address range. Only probes that pass this filter undergo full evaluation. This partial approach maintains accuracy for relevant probes while avoiding the overhead of fully evaluating every probe, thus resolving the contradiction between evaluation accuracy and throughput.
Solution Approach 2:
The probe handling process is segmented into distinct stages: initial filter evaluation, full probe evaluation, and responsive action execution. By dividing the monolithic evaluation process into segments, the system can quickly discard irrelevant probes without committing full processing resources, thereby improving throughput while maintaining accuracy for probes that require detailed evaluation.
2Reliability
If hardware resources are dedicated to evaluating every invalidation probe, then the reliability of cache coherency is improved, but the hardware complexity and resource usage increase
Solution Approach 1:
The hardware architecture is segmented into a filter evaluation unit and a full evaluation unit. The filter unit handles preliminary checks for all probes, while the full evaluation unit processes only those probes that pass the filter. This segmentation reduces the hardware burden on any single component while maintaining overall system reliability.
Solution Approach 2:
The filter evaluation acts as an intermediary between the incoming probe and the full evaluation hardware. It pre-processes probes and selectively passes only relevant ones to the expensive full evaluation unit, thereby reducing the need for dedicated hardware resources while preserving cache coherency reliability.
3Reliability
If overinclusive actions are taken for invalidation probes, then the cache coherency is maintained, but the resource wastage and unnecessary operations increase
Solution Approach 1:
The patent avoids overinclusive actions by implementing precise address range filtering. Instead of taking actions for all probes or using broad invalidation ranges, the filter evaluation accurately determines whether each probe target actually falls within cached addresses. This enables selective processing that maintains cache coherency only when necessary, reducing energy waste from unnecessary operations.
Solution Approach 2:
The system applies different handling qualities to different probes based on their characteristics. Probes that target cached addresses receive full evaluation and appropriate actions, while probes targeting non-cached addresses are quickly filtered out. This local differentiation ensures cache coherency is maintained where needed without wasting resources on unnecessary operations elsewhere.
Data Source
AI summary
Systems and methods selectively filter, buffer, and process cache coherency probes. A processor includes a probe buffering unit that includes a cache coherency probe buffer. The probe buffering unit receives cache coherency probes and memory access requests for a cache. The probe buffering unit identifies and discards any of the probes that are directed to a memory block that is not cached in the cache, and buffers at least a subset of the remaining probes in the probe buffer. The probe buffering unit submits to the cache, in descending order of priority, one or more of: any buffered probes that are directed to the memory block to which a current memory access request is also directed; any current memory access requests that are directed to a memory block to which there is not a buffered probe also directed; and any buffered probes when there is not a current memory access request.