Probe Card Levelness Adjustment via Alignment Marks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional probe cards face inaccuracies in testing due to the potential misalignment of probe pins, which can lead to incomplete contact with conductive leads of a device under test, resulting in unreliable testing results.
Innovation Solution
A method and system utilizing a probe card with a circuit board featuring a reference plane and non-collinear alignment marks, allowing for precise leveling adjustments to ensure the probe pins are parallel to the wafer-loading plane, ensuring complete contact and accurate testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the probe card levelness is measured based on a virtual plane defined by pinpoints of the probe pins, then the measurement can be performed, but the virtual plane may be indefinite when probe pins are not aligned levelly, leading to inaccurate levelness measurement and unreliable testing results
Solution Approach 1:
The patent introduces alignment marks as an intermediary reference element on the circuit board to define a reference plane. This intermediary provides a stable, predefined geometric reference that is independent of the probe pin positions, enabling accurate levelness measurement even when probe pins are misaligned. The alignment marks serve as a mediator between the probe card structure and the measurement process, eliminating the dependency on probe pin alignment for establishing a reference plane.
2Ease of manufacture
If the probe pins are not aligned levelly with each other, then the probe card structure can be simpler to manufacture, but the virtual plane becomes indefinite and the probe card cannot be guaranteed to contact all conductive leads properly
Solution Approach 1:
The patent separates the reference plane definition function from the probe pin array structure. By placing alignment marks directly on the circuit board's reference plane, the levelness reference is segmented independently from the probe pin positions. This allows the probe pins to be manufactured without strict alignment requirements while the alignment marks provide the necessary geometric reference for leveling the entire probe card assembly.
3Measurement precision
If alignment marks are added to the circuit board, then the levelness measurement accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent merges the alignment marks directly onto the circuit board's reference plane, combining the levelness reference function with the existing circuit board structure. This integration approach avoids adding separate, complex leveling mechanisms while still providing the necessary geometric reference. The alignment marks become an inherent part of the circuit board design rather than an additional independent component.
Data Source
AI summary
A method for utilizing a probe card includes steps as follows. Providing a probe card having three alignment marks on a reference plane of a circuit board; moving the circuit board to be oriented to a wafer-loading plane of a wafer stage with the reference plane; determining whether a geometric plane defined by the alignment marks is parallel to the wafer-loading plane; and when the geometric plane is not parallel to the wafer-loading plane, adjusting a levelness of the circuit board until the reference plane is parallel to the wafer-loading plane.