Probe Card Open-End Segmentation for Signal Delay Measurement
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Solution Overview
Problem
Conventional test apparatuses face difficulties in generating accurate multiple-valued test signals for semiconductor devices due to variations in transmission path delays, which prevents precise timing adjustments and accurate signal combination using existing driver/comparator pins.
Innovation Solution
The test apparatus employs a configuration where drivers output signals to a common terminal via probe pins with open top ends, allowing for measurement and adjustment of signal timings using TDR, and combines these signals to generate multiple-valued test signals by keeping probe pins electrically open when not testing, enabling accurate multiple-valued signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If driver/comparator pins are used to generate binary test signals for creating multiple-valued test signals, then cost is reduced by reusing existing pins, but measurement precision of transmission path delays deteriorates because the top ends of transmission paths are short-circuited and cannot be accessed for TDR measurement
Solution Approach 1:
The transmission path is segmented into two parts: the main transmission path through the probe card, and a measurement path through the open top end of the probe pin. This segmentation allows independent measurement of transmission path delay without affecting the signal combination function, resolving the contradiction between cost efficiency and measurement capability
Solution Approach 2:
The open top end of the probe pin serves as an intermediary measurement point that provides access to the transmission path for TDR measurements. This intermediary point enables delay measurement without requiring modification to the driver/comparator pin configuration, maintaining cost efficiency while enabling precise measurement
2Device complexity
If transmission paths have different delay amounts, then device complexity is reduced by using existing driver/comparator pins, but reliability of multiple-valued signal generation deteriorates due to inaccurate signal combination timing
Solution Approach 1:
The transmission path delay is measured in advance using TDR through the open probe pin top ends before signal combination. This preliminary measurement allows for timing compensation and adjustment, ensuring accurate signal combination even with different path delays, thus maintaining reliability without increasing device complexity
Solution Approach 2:
The measured transmission path delay information provides feedback for adjusting the timing of signal combination. This feedback mechanism enables dynamic timing adjustment to compensate for path delay variations, ensuring accurate multiple-valued signal generation while using simple existing pin configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the generation of accurate multiple-valued test signals by adjusting driver signal timings based on measured delays, overcoming the limitations of conventional methods and ensuring precise testing of semiconductor devices.
Implementation Method 1
The test apparatus measures the delay amounts of the transmission paths by using a time domain reflectometry (TDR) method
Implementation Method 2
measures the delay time of a transmission path by inputting a signal into the transmission path with its top end being kept open and measuring the delay time of the signal which is reflected at the open top end of the transmission path
Data Source
AI summary
There is provided a test apparatus for testing a device under test. The test apparatus includes a plurality of drivers that respectively output a plurality of test signals to a same terminal of the device under test so as to supply, to the same terminal of the device under test, a multiple-valued signal that is generated by combining together the plurality of test signals, and a plurality of probe pins that are provided in a one-to-one correspondence with the plurality of drivers. Here, each of the plurality of probe pins has a top end portion to be electrically connected to the same terminal of the device under test so as to supply a signal output from a corresponding one of the plurality of drivers to the same terminal of the device under test while the test apparatus is testing the device under test, and the top end portion of each probe pin is kept electrically open while the test apparatus is not testing the device under test.