Probe Card Partition Scheme for High Pin Count IC Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated circuit (IC) testing is constrained by high pin counts, leading to increased testing time and cost due to the need for multiple probe card insertions and customized probe cards, which are expensive.
Innovation Solution
The method involves repartitioning probe card layouts to reduce the number of distinct sections, allowing a single probe card to be reused multiple times, with dummy pads added for uniformity and alignment marks for efficient testing within a tester pin count limit, thereby reducing the number of probe cards and wafer insertions required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If customized probe cards are used for high pin count IC testing, then testing capability is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent creates a universal probe card design that can test multiple IC packages with different pin counts (e.g., BGA, CSP, QFN) using the same card. The card incorporates reusable probe elements that can be positioned to contact different pin configurations, eliminating the need for customized probe cards for each IC type and reducing manufacturing costs while maintaining testing capability.
Solution Approach 2:
The probe card is divided into multiple independent probe elements or sections that can be selectively activated or positioned. This segmentation allows a single probe card to handle different pin count requirements by engaging only the necessary probe elements, thereby reducing the need for fully customized cards for each IC package type.
2Reliability
If multiple probe cards are used to test high pin count ICs, then testing completeness is improved, but testing time increases
Solution Approach 1:
The universal probe card allows all necessary probe contacts to be made in a single insertion, eliminating the need for multiple sequential insertions. The card is designed with probe elements distributed across different zones that can simultaneously contact pins in various IC configurations, achieving complete testing in one operation and reducing testing time.
Solution Approach 2:
The probe card utilizes a two-dimensional arrangement of probe elements that can contact multiple pins simultaneously across the IC package surface. This spatial distribution allows comprehensive testing to be achieved in a single insertion event rather than requiring multiple sequential insertions, thereby reducing testing time while maintaining completeness.
3Adaptability or versatility
If multiple wafer insertions are performed for testing, then coverage of high pin count ICs is improved, but productivity decreases
Solution Approach 1:
The universal probe card is designed to accommodate multiple IC package types and pin counts within a single wafer insertion event. By integrating probe elements that can contact various pin configurations simultaneously, the system achieves comprehensive coverage without requiring multiple wafer insertions, thereby maintaining high productivity and testing throughput.
Data Source
AI summary
A method of testing an integrated circuit die comprises partitioning a first probe card partition layout of the integrated circuit die having one or more sections comprising a first quantity of section types into a second probe card partition layout having a greater quantity of sections comprising a second quantity of section types, the second quantity of section types being less than the first quantity of section types. The method also comprises using one or more probe cards to test the sections in the second probe card partition layout, each of the one or more probe cards having a test contact pattern that corresponds with a test contact pattern of one of each section type included in the second probe card partition layout.