Semiconductor Probe Card Segmentation for Parallel Chip Testing
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Solution Overview
Problem
Current semiconductor testing apparatuses require multiple contacts with a probe card to test wafers, leading to increased test time and reduced productivity.
Innovation Solution
A testing apparatus and method utilizing a probe card with signal transmitters that simultaneously supply power supply voltage to selected chips and sequentially transfer test voltages from the chips to a test controller, allowing for efficient chip selection, power supply, and defect determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple contacts with the probe card are used to test wafers, then comprehensive testing can be performed, but test time increases and productivity decreases
Solution Approach 1:
The probe card is divided into multiple independent test blocks (first test block, second test block, etc.), each capable of testing different chips simultaneously. This segmentation allows parallel testing of multiple chips, reducing total test time while maintaining comprehensive testing coverage.
Solution Approach 2:
Multiple test blocks are combined into a single probe card assembly that can perform multiple testing operations simultaneously. The test controller coordinates these blocks to test multiple chips in parallel, merging the functionality of what would otherwise require sequential operations.
2Productivity
If all chips are tested simultaneously, then productivity improves, but control and signal management complexity increases
Solution Approach 1:
The probe card is divided into multiple independent test blocks, each with its own signal transmitters and control signals. This segmentation simplifies the control architecture by creating modular, independently controllable units, making signal management more manageable despite testing multiple chips in parallel.
Solution Approach 2:
The system dynamically activates specific test blocks based on testing requirements. The test controller can selectively enable or disable individual test blocks and their corresponding signal transmitters, providing flexible control that adapts to different testing scenarios and reduces unnecessary signal complexity.
Data Source
AI summary
A testing apparatus includes a test controller configured to output a plurality of chip selection signals for selecting chips to be tested from among a plurality of chips, a plurality of first control signals for controlling supply of a power supply voltage to the chips selected by the chip selection signals, and a plurality of second control signals for controlling receiving of test voltages output from the chips supplied with the power supply voltage, and a probe card including one or more test blocks each having a plurality of signal transmitters configured to respectively transfer the power supply voltage to the corresponding chips in response to the different first control signals and respectively apply the test voltages output from the corresponding chips to the test controller in response to the different second control signals.