Probe Contact Detection Logic for Semiconductor Test Yield
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Solution Overview
Problem
During semiconductor device testing in parallel configurations, misalignment of probe needles with terminals or pins can lead to open circuits, causing unnecessary device failures and reducing production efficiency and yield.
Innovation Solution
Incorporating test logic circuitry that performs a probe contact detection test using probe signals and external supply voltages to verify electrical contact between probe needles and terminals, configuring input buffers for single-ended operation, and using logic gates to indicate the presence of open circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor devices are connected to a test setup in parallel for highly parallel testing, then productivity is improved, but the risk of probe needle misalignment causing open circuits increases
Solution Approach 1:
The patent applies preliminary action by performing a probe contact detection test before conducting the actual device functionality test. The test logic circuitry detects whether each terminal is properly contacted by a probe needle in advance, allowing misaligned probes to be identified and corrected before the main testing process begins, thus preventing false failures while maintaining high parallel testing throughput
2Productivity
If probe needles are positioned to contact terminals during parallel testing, then testing efficiency is improved, but misalignment may cause open circuits leading to false device failures
Solution Approach 1:
The patent implements feedback by using the output signal from the test logic circuitry to indicate whether proper contact exists between probe needles and terminals. This feedback mechanism allows the testing system to detect contact status and adjust probe positioning or identify misaligned connections, ensuring accurate contact detection while maintaining efficient parallel testing operations
3Reliability
If a probe contact detection test is performed using test logic circuitry, then false-positive errors are reduced, but device complexity increases
Solution Approach 1:
The patent applies universality by designing test logic circuitry that can be integrated into the existing semiconductor device structure and serves multiple functions: detecting probe contact status, generating output signals for contact verification, and working with existing input buffers and logic gates. This multi-functional approach reduces false-positive errors without requiring entirely separate additional testing equipment, thereby limiting the increase in overall device complexity
Data Source
AI summary
An example apparatus includes an input buffer coupled to an input terminal, wherein the input buffer is configured to provide an input signal based on a voltage received at the input terminal, a test terminal configured to receive a probe signal, and a power supply terminal configured to receive an external supply voltage. The example apparatus further includes a test logic circuit configured to, in response to the probe signal indicating a test and an external supply voltage detection signal having a value indicating detection of the external supply voltage, initiate a probe contact detection test. During the initiate a probe contact detection test, the test logic circuit is configured to receive the input signal and to provide an output signal having a value based on the input signal.