Probe Filtering via Inclusion and Victim Bits
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Solution Overview
Problem
In processor-based systems with distributed cache memory, the current methods for filtering probes to shared caches result in unnecessary probes and performance degradation due to the inability to accurately determine which underlying L1 caches contain a requested cache line, especially when multiple L1 caches are associated with a single core.
Innovation Solution
Implementing a method that uses inclusion bits and a victim probe bit to filter probes, where each cache line is associated with a set of inclusion bits indicating residency in different subsets of L1 caches and an additional victim probe bit indicating residency in more than one cache, allowing for efficient filtering and reducing unnecessary probes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional probe filtering methods are used in distributed cache systems, then cache coherence is maintained, but unnecessary probes are generated causing performance degradation
Solution Approach 1:
The probe filtering mechanism is segmented into multiple independent components: inclusion bits for each L1 cache subset, victim probe bits for tracking multi-cache residency, and filter logic that processes probes selectively. This segmentation allows the system to maintain cache coherence through targeted filtering while avoiding unnecessary probes to caches that don't contain the requested line, thus resolving the contradiction between reliability and productivity.
Solution Approach 2:
The system performs preliminary actions by pre-setting inclusion bits when cache lines are loaded into L1 caches and pre-tracking residency status with victim probe bits before external probes arrive. This preliminary preparation enables the filter logic to quickly determine which caches need to service probes, eliminating unnecessary probe traffic and improving probe processing efficiency while maintaining coherence.
2Reliability
If all L1 caches service external probes, then cache coherence is ensured, but latency increases due to unnecessary cache accesses
Solution Approach 1:
The probe filtering system applies local quality by treating each L1 cache subset differently based on its actual residency status. Inclusion bits track which specific caches contain each cache line, allowing the filter logic to selectively service only those caches with local quality relevance to the probe, rather than broadcasting to all caches uniformly. This reduces latency by eliminating unnecessary accesses to caches that don't contain the requested line.
Solution Approach 2:
The system uses feedback mechanisms where inclusion bits and victim probe bits provide real-time information about cache line residency status back to the filter logic. This feedback enables dynamic decision-making: when an external probe arrives, the filter logic queries the inclusion/victim probe bits to determine which caches actually need to respond, thereby reducing probe service latency while ensuring coherence is maintained for caches that do contain the line.
3Measurement precision
If inclusion bits track residency in all L1 caches, then probe filtering accuracy improves, but device complexity increases
Solution Approach 1:
The system resolves the complexity-accuracy tradeoff by adding another dimension to the cache control structure: victim probe bits that track whether a cache line resides in more than one L1 cache within a subset. This dimensional addition allows the filter logic to make accurate filtering decisions with fewer inclusion bits needed, as the victim probe bit provides aggregate information about multi-cache residency, thereby improving probe filtering accuracy without proportionally increasing device complexity.
Solution Approach 2:
The inclusion bits and victim probe bits serve multiple functions: they track cache line residency, enable probe filtering decisions, and provide information about multi-cache coherence scenarios. This multi-functionality reduces the need for separate dedicated structures for each function, allowing the system to achieve high probe filtering accuracy with a relatively compact control structure, thus balancing measurement precision with device complexity.
Data Source
AI summary
A method and apparatus use one or more inclusion bits and a victim bit to filter probes to shared caches. One embodiment of the method includes filtering a probe or snoop of one or more of a plurality of first caches based on a plurality of first bits, such as inclusion bits, associated with a line indicated by the probe or snoop. Each of the plurality of first bits is associated with a different subset of the plurality of first caches and each first bit indicates whether the line is resident in a corresponding subset of the plurality of first caches. A second bit, such as a victim probe bit, indicates whether the line is resident in more than one of the plurality of first caches in at least one of the subsets of the plurality of first caches. The first caches may be L1 caches and the first bits may be stored in an L2 cache of a multilevel cache.