Semiconductor Probe Head Abnormality Detection via Statistical Analysis
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Solution Overview
Problem
Existing semiconductor device inspection methods fail to detect probe head abnormalities during initial inspections, leading to erroneous classification of non-defective devices as defective, as the non-defective rate for each probe block is calculated post-inspection, preventing early detection of probe head issues.
Innovation Solution
A device inspection apparatus with a housing, multiple probe heads, an inspection unit, a storage unit, an analysis unit for statistical processing of inspection data, and a warning unit to indicate abnormal probe heads, allowing for real-time detection of significant differences in inspection results across probe heads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the non-defective rate for each probe block is calculated after all chips are inspected, then the erroneous determination can be reduced through re-inspection, but the abnormality of probe block cannot be detected during the first inspection
Solution Approach 1:
The patent performs preliminary actions by calculating the non-defective rate for each probe block immediately after inspecting chips with that probe block, rather than waiting until all chips are inspected. This allows abnormal probe blocks to be identified and flagged during the inspection process itself, enabling timely re-inspection or replacement while maintaining high inspection accuracy without delaying the overall process
2Productivity
If multiple probe blocks are used for parallel inspection to increase throughput, then productivity is improved, but contact resistance increases leading to more erroneous defective determinations
Solution Approach 1:
The patent implements feedback by continuously monitoring the non-defective rate for each probe block during parallel inspection operations. When the non-defective rate for a probe block falls below a predetermined threshold, the system automatically identifies that probe block as abnormal and triggers re-inspection or replacement actions, thereby maintaining high determination accuracy while preserving the productivity benefits of parallel inspection
Solution Approach 2:
The patent dynamically adjusts the inspection process by changing operational parameters based on probe block performance. Specifically, when a probe block's non-defective rate drops below the threshold, the system modifies the inspection workflow for chips inspected by that probe block, directing them to re-inspection with a different probe block, thus adapting the inspection parameters to maintain accuracy across high-throughput parallel operations
Data Source
AI summary
A device inspection apparatus comprises: a plurality of probe heads; an inspection circuitry to measure inspection value data for each semiconductor device; a storage circuitry to store inspection result data including the inspection value data and a determination result on the semiconductor device; and an analysis circuitry to perform, by statistical processing based on a plurality of the inspection result data present for each inspection item and stored in the storage circuitry, an analysis to determine if there is a significant difference between a plurality of the inspection result data for each of the probe heads, and determines that a probe head concerned is abnormal if there is a significant difference.