Dynamic Probe Location Selection for Parasitic Resistance Extraction
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Solution Overview
Problem
As technology scales down to 14 nm and below, ESD protection devices become larger compared to logic devices, and thin metal layers increase interconnect resistance, making fast parasitic resistance extraction challenging without affecting accuracy.
Innovation Solution
The method involves automatically moving probe locations on a layout design to identify new probe locations based on geometric elements within a predetermined area or distance from the original probe location, conducting ESD analysis, and extracting parasitic resistance values for effective ESD protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional parasitic extraction methods are used with fixed probe locations, then extraction speed is maintained, but accuracy deteriorates due to increased interconnect resistance from thin metal layers
Solution Approach 1:
The probe location is made dynamic rather than fixed. The system automatically determines optimal probe locations based on the extracted geometric elements and their conductive connections, allowing the probe position to adapt to the specific layout geometry and achieve accurate parasitic resistance extraction
Solution Approach 2:
The system performs self-verification by checking conductive connections and validating that the selected probe location candidates are properly connected to the original probe location through the layout geometry, ensuring extraction accuracy without external intervention
2Measurement precision
If probe locations are automatically moved to geometric elements, then parasitic resistance extraction accuracy is improved, but extraction time increases
Solution Approach 1:
The extraction process is segmented into distinct steps: identifying geometric elements, determining probe location candidates based on proximity and area criteria, verifying conductive connections, and selecting final probe locations. This segmentation allows systematic processing while maintaining accuracy
Solution Approach 2:
The system performs preliminary identification of probe location candidates before final selection, using predetermined area and distance criteria to narrow down options. This preliminary action streamlines the subsequent extraction process by pre-validating candidate locations
3Reliability
If ESD protection devices are sized larger to meet protection targets, then ESD protection capability is improved, but device area increases compared to logic devices
Solution Approach 1:
The patent replaces physical measurement and manual probe placement with an automated computational system that uses geometric element analysis and conductive connection verification to determine optimal probe locations, eliminating manual intervention
Solution Approach 2:
The system changes the probe location parameter dynamically based on layout geometry analysis, selecting different probe positions for different ESD structures based on their specific geometric elements and conductive connection patterns
Data Source
AI summary
Probe location candidates for parasitic extraction are identified from geometric elements on a probe layer. The probe layer is a physical layer of a layout design for a circuit design predetermined for placing one or more new probes. The probe location candidates are geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value. Moreover, the probe location candidates are conductively connected to the original probe location. One or more new probe locations on the probe location candidates are selected based on predetermined criteria. From the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations is extracted.