Semiconductor Cover Layers for Probe Mark Stress Relief

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Solution Overview

Problem

The semiconductor industry faces challenges with probe marks on test pads, which can lead to reliability issues and failure during die stacking due to high-stress cover layers causing voids and cracks, restricting the placement of interconnects and bonding elements.

Innovation Solution

A multi-layer protective structure with a low-stress oxide first cover layer and a high-stress oxide second cover layer is formed to fill and protect probe marks, improving compatibility and mechanical durability, and a third cover layer is added for additional protection and bonding during die stacking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If a high-stress oxide cover layer is formed to protect the test pad, then mechanical strength is improved, but voids and cracks are generated due to stress incompatibility

Engineering Contradiction:

Improvemechanical strengthVSAvoidreliability

Core Design Contradiction:

StrengthVSReliability

Solution Approach 1:

The cover layer is divided into multiple segments: a first cover layer (low-stress oxide) and a second cover layer (high-stress oxide). This segmentation allows each layer to perform its specific function - the first layer provides stress relief while the second layer provides mechanical protection, resolving the contradiction between strength and reliability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent uses a composite structure combining low-stress oxide and high-stress oxide materials in the cover layer. This composite approach allows the system to simultaneously achieve low stress (from the first layer) and high mechanical strength (from the second layer), eliminating voids and cracks while maintaining protection

Inventive Principle:

Principle #40Composite materials

2Ease of operation

If probe marks are left on test pads for testing, then testing capability is maintained, but design restrictions occur for interconnect and bonding element placement

Engineering Contradiction:

Improvetesting capabilityVSAvoiddesign flexibility

Core Design Contradiction:

Ease of operationVSAdaptability or versatility

Solution Approach 1:

The harmful effect of probe marks is extracted and isolated by filling them with the first cover layer material. This removes the probe marks as design restrictions while preserving the test pad functionality, allowing interconnects and bonding elements to be placed freely in the previously restricted areas

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The probe marks, which were previously harmful by restricting design, are converted into beneficial filled structures. The first cover layer material fills the probe marks, transforming them from design obstacles into integrated parts of the protective cover structure, enabling full design flexibility

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS20250006564A1Semiconductor structures with cover layers

Publication Date: 2025.01.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Semiconductor structures, die stack structures, and fabrication methods are provided. In one example, a semiconductor structure includes a die having a test pad disposed on a front side of the die. The test pad has a probe mark in an upper portion of the test pad. The probe mark has an open end at a top surface of the test pad, a bottom wall, a sidewall connected to the bottom wall, and a space between the open end, the bottom wall and the sidewall. The semiconductor structure further includes a first cover layer and a second cover layer. The first cover layer is disposed on the front side of the first test pad and the sidewall and the bottom wall of the probe mark. The second cover layer is disposed on the first cover layer. The first and second cover layers comprise different materials.