Prober LED Heating Segments Wafer Thermal Load
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Solution Overview
Problem
In semiconductor device manufacturing, the probe test for IC chips on a wafer faces challenges in accurately identifying defective chips due to thermal load issues, where the heat generated by test target chips affects neighboring chips, leading to insufficient defect detection before packaging.
Innovation Solution
A prober system with LED units on the opposite side of the stage independently heats test target chips and their peripheral areas, allowing for precise temperature control and reduced thermal load on non-test target chips by using a controller to manage LED unit activation based on the test target chip's location.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a heater is used to control the temperature of the entire wafer surface, then the temperature can be maintained for mounting environment simulation, but the thermal load affects non-test target chips causing insufficient defect detection
Solution Approach 1:
The heater is divided into multiple independent heating regions corresponding to different chip locations on the wafer. Each heating region can be independently controlled to apply heat only to the specific chip being tested and its immediate vicinity, rather than heating the entire wafer surface uniformly. This segmentation allows temperature control for the test chip while minimizing thermal load on non-test chips.
Solution Approach 2:
The heating system provides localized temperature control with different thermal conditions for different regions of the wafer. The test target chip region receives sufficient heat to simulate mounting environment, while non-test chip regions receive minimal or no heat. This local quality approach ensures each chip experiences appropriate thermal conditions for its specific test status.
2Measurement precision
If the same voltage as mounting voltage is applied to the test target chip, then accurate electrical characteristic testing is achieved, but excessive heat is generated affecting surrounding chips
Solution Approach 1:
The harmful thermal effect generated by applying high voltage to the test chip is extracted and isolated by providing dedicated localized heating to non-test chips. This compensates for the thermal impact and prevents heat accumulation that would affect surrounding chips, allowing full mounting voltage to be applied for accurate testing without thermal interference to other chips.
Solution Approach 2:
The heat generated by the test chip during high-voltage testing, which would normally be a harmful effect, is converted into a beneficial localized heating source. By adding supplemental localized heating to non-test chips, the system uses the test chip's thermal output to help maintain appropriate temperature conditions for adjacent chips, transforming the harmful thermal load into a useful thermal contribution.
3Object-affected harmful factors
If cooling is applied to the entire wafer surface, then thermal load is reduced, but the temperature cannot be maintained for mounting environment simulation
Solution Approach 1:
The temperature control system is segmented into multiple independent zones with separate heating and cooling control for each chip location. This allows non-test chips to be actively cooled to reduce thermal load, while the test chip region maintains heating to simulate mounting environment temperature. Each zone can operate with different thermal conditions simultaneously.
Solution Approach 2:
The thermal control system dynamically adjusts heating and cooling based on real-time test requirements. During testing, the system switches from uniform heating to localized heating combined with selective cooling. The cooling intensity and heating intensity are dynamically regulated to maintain thermal balance, ensuring non-test chips are protected from excessive heat while the test chip experiences appropriate thermal conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces thermal load on non-test target chips, enabling more accurate electrical characteristic testing and defect identification during the probe test without overheating adjacent IC chips.
Implementation Method 1
a plurality of LED units provided on a side opposite to a placing surface of the stage so as to independently heat a plurality of areas where the plurality of test target chips are located, respectively, and each including one or a plurality of LEDs
Implementation Method 2
an LED unit corresponding to an area of a test target chip on which the test is performed, among the area of the test target chip on which the test is performed and peripheral areas of the corresponding area
Data Source
AI summary
A prober includes: a stage that places a substrate formed with a plurality of chips thereon in a matrix; a contact that sequentially contacts with electrode pads of the plurality of chips thereby performing an inspection on electrical characteristic of the plurality of chips; a plurality of LED units provided on a side opposite to a placing surface of the stage so as to independently heat a plurality of areas where the plurality of chips are located, respectively, and each including one or a plurality of LEDs; and a controller that outputs a control signal to drive, among the plurality of LED units, at least an LED unit corresponding to an area of a chip to be inspected, among the area of the chip to be inspected and peripheral areas of the corresponding area.