Prober Multistage Structure for Wafer Parallelism
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Solution Overview
Problem
Existing semiconductor probers face challenges in maintaining parallelism between the probe card and wafer during wafer-level inspection, leading to reduced measurement accuracy due to deformation of the head stage under test head load and unbalanced wafer chuck alignment, which increases installation area and device cost while decreasing throughput.
Innovation Solution
A prober with a multistage structure incorporating a pogo frame, suction fixing parts, a mechanical lifting unit, and a guide unit to maintain parallelism and prevent deformation, ensuring accurate contact between probes and electrode pads through a combination of suction fixation and pressure reduction in an air-tight space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of probes is increased to perform multiple probing for simultaneous inspection of multiple chips, then throughput is improved, but position accuracy when moving the probe decreases
Solution Approach 1:
The patent transitions from a single-stage probe card structure to a multistage structure where probe cards are arranged in multiple stages (e.g., upper and lower stages). This spatial arrangement in the vertical dimension allows simultaneous inspection of multiple chips without compromising positioning accuracy, as each stage can be independently positioned and controlled.
Solution Approach 2:
The probe card is divided into multiple independent probe units arranged in different stages. Each probe unit can be independently positioned and controlled, allowing parallel inspection of multiple chips while maintaining precise positioning for each individual probe-chip contact.
2Productivity
If a multistage structure with stacked measuring sections is adopted to increase throughput, then installation area is reduced, but device complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking measuring sections in multiple stages (e.g., upper and lower stages). This allows multiple inspection operations to be performed simultaneously within a compact footprint, increasing throughput while minimizing the horizontal installation area.
Solution Approach 2:
Multiple measuring sections are combined in a vertically stacked configuration, sharing common support structures and control systems. This merging approach increases throughput by enabling parallel inspection while reducing overall device complexity through shared components and integrated control.
3Device complexity
If the test head is directly mounted on the head stage, then device complexity is reduced, but the head stage deforms under load and measurement accuracy decreases
Solution Approach 1:
A pogo frame is introduced as an intermediary component between the test head and the head stage. This pogo frame serves as a mechanical mediator that distributes the load from the test head, preventing direct mounting deformation and maintaining the parallelism accuracy between the probe card and wafer surface.
4Measurement precision
If suction fixation is used to integrate the test head, pogo frame, probe card, and wafer chuck, then positioning accuracy is improved, but the system requires an air-tight space and pressure reducing unit
Solution Approach 1:
The patent employs suction fixation using a pressure reducing unit to create a vacuum environment within an air-tight space. This pneumatic fixation method achieves high positioning accuracy by uniformly attracting and holding the test head, pogo frame, probe card, and wafer chuck in precise alignment, with the seal member maintaining the required air-tight condition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances measurement accuracy by preventing deformation and maintaining parallelism between the probe card and wafer, improving inspection efficiency while minimizing installation area and device cost.
Implementation Method 1
a first suction fixing part that fixes the test head and the pogo frame to each other by suction; a second suction fixing part that fixes the probe card and the pogo frame to each other by suction
Implementation Method 2
a pressure reducing unit configured to reduce pressure in the air-tight space to allow the wafer chuck to be drawn toward the probe card
Data Source
AI summary
Provided is a prober capable of maintaining parallelism between a probe card and a wafer as well as performing wafer-level inspection with high accuracy. A test head is held by a test head holding part, and the test head and a probe card are sucked and fixed to a pogo frame attached to a head stage. A wafer chuck is moved toward a probe card while being fixed to a Z-axis movement-rotation unit in a detachable manner, and the wafer chuck is drawn toward the probe card by reducing pressure in an air-tight space formed between the wafer chuck and the probe card using a pressure reducing unit. Then, an electrical inspection of a wafer is performed while the test head, the pogo frame, the probe card, and the wafer chuck are integrated with respect to the head stage.