Probing Chips During Package Formation for 3DIC Yield

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Solution Overview

Problem

Three-Dimensional Integrated Circuits (3DICs) face manufacturing yield losses due to connector cracking, delamination, and severe warpage in wafers, which complicates the manufacturing process.

Innovation Solution

A novel 3DIC package manufacturing method involving the formation of through-substrate vias, front-side and backside interconnect structures, and a probing process to identify and separate defective packages early, preventing further yield loss by bonding only good packages to subsequent components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If wafer-level packaging is used to improve productivity, then manufacturing throughput increases, but warpage and connector reliability issues worsen

Engineering Contradiction:

Improvemanufacturing throughputVSAvoidconnector reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements probing and testing operations at intermediate stages during wafer-level packaging to identify and isolate defective packages before final assembly. This preliminary detection prevents defective connectors from propagating through subsequent manufacturing steps, thereby maintaining both high throughput and improved reliability.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediate testing and probing stage that acts as a mediator between the wafer-level packaging process and final assembly. This intermediary step separates good packages from defective ones, allowing continuous high-volume manufacturing while filtering out reliability issues before they affect the final product.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If wafer-level packaging is used to improve productivity, then manufacturing throughput increases, but warpage issues worsen

Engineering Contradiction:

Improvemanufacturing throughputVSAvoidwafer warpage

Core Design Contradiction:

ProductivityVSShape

Solution Approach 1:

The patent performs probing and structural assessments at intermediate stages to detect warpage and other structural defects early in the wafer-level packaging process. By identifying warped wafers before final assembly, the method prevents warpage from compounding through subsequent manufacturing steps, maintaining both productivity and structural integrity.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If intermediate probing and separation of defective packages is implemented, then manufacturing yield improves, but process complexity increases

Engineering Contradiction:

Improvemanufacturing yieldVSAvoidprocess complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the wafer-level packaging process into distinct stages: initial bonding, intermediate probing/testing, separation of defective packages, and final assembly. This segmentation allows for targeted quality control at critical points without requiring complete process redesign, thereby improving yield while managing complexity through modular process organization.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9006004B2Probing chips during package formation

Publication Date: 2015.04.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.