Process Allocation for Hybrid Memory Systems

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Solution Overview

Problem

In information processing systems with hybrid memory configurations that include both DRAM and PM, conflicts between processes accessing DRAM and PM can lead to performance degradation due to differences in process speeds and access frequencies, making it challenging to optimize process allocation effectively.

Innovation Solution

A processor with a memory controller that determines process allocation based on the characteristics of each process, such as memory access frequency and access patterns, to minimize conflicts and optimize performance by allocating processes that cause performance degradation to different CPU sockets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If processes accessing DRAM and PM are executed in parallel in a single processor, then process throughput is increased, but process performance degrades due to conflicts in the memory controller

Engineering Contradiction:
Improveprocess throughputVSAvoidprocess performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments processes into two categories: first processes that frequently access DRAM and second processes that frequently access PM. The allocation determination unit assigns first processes to first processors (optimized for DRAM) and second processes to second processors (optimized for PM), preventing conflicts in the memory controller while maintaining high throughput by utilizing both memory types in parallel across different processors

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If a memory controller controls both DRAM and PM, then memory capacity is increased, but access speed decreases due to the slower PM

Engineering Contradiction:
Improvememory capacityVSAvoidaccess speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent applies local quality by creating different processor types with specialized memory controller configurations: first processors are optimized for DRAM access while second processors are optimized for PM access. This allows each processor type to operate at optimal speeds for its designated memory type, maintaining high access speed while utilizing the combined capacity of both DRAM and PM across the system

Inventive Principle:
Principle #3Local quality

3Ease of operation

If processes are allocated without considering memory access characteristics, then allocation simplicity is maintained, but memory controller conflicts increase

Engineering Contradiction:
Improveallocation simplicityVSAvoidmemory controller conflicts
Core Design Contradiction:
Ease of operationVSObject-generated harmful factors

Solution Approach 1:

The patent implements preliminary action by having the allocation determination unit analyze process characteristics and determine optimal processor allocation before processes are executed. By pre-classifying processes based on their memory access patterns and assigning them to appropriate processors, the system prevents memory controller conflicts before they occur, maintaining both simplicity and effectiveness

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11487582B2Information processing apparatus and computer-readable recording medium having stored therein process allocation determining program
Publication Date: 2022.11.01 FUJITSU LTD
  • US11487582B2 patent drawing
  • US11487582B2 patent drawing
  • US11487582B2 patent drawing

AI summary

An information processing apparatus including a plurality of groups, each group including a first memory, a second memory different in process speed from the first memory, and a processor including a memory controller that is connected to the first memory and the second memory and that controls an access from a process to the first memory and the second memory, wherein a first processor among a plurality of the processors of the plurality of groups is configured to determine, based on a characteristic of a plurality of the processes accessing data stored in the first memory or the second memory in each of the plurality of groups, an allocation of the plurality of processes onto the plurality of processors.