Process Compensated Delay Line for Constant Circuit Timing
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Solution Overview
Problem
Semiconductor circuits face significant delay variations across different process corners due to physical factors like gate oxide thickness and doping concentrations, affecting transistor performance and circuit speed.
Innovation Solution
A delay equalizer circuit that uses a process monitor to sense the operating process corner and outputs bias voltages to regulate delay through a current-starved delay chain, compensating for variations by generating pMOS and nMOS reference currents to maintain constant delay across process corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple CMOS-based inverter chain is used to implement delay, then the device complexity is low, but the delay varies significantly across process corners
Solution Approach 1:
The patent changes the electrical parameters (bias currents, voltages) of the delay line based on detected process conditions. Process corners are detected by measuring threshold voltages of monitor transistors, and bias currents are adjusted accordingly to compensate for process variations, maintaining consistent delay across different process corners
Solution Approach 2:
The patent implements a feedback mechanism where process corners are continuously detected through monitor transistors, and the detected information is used to adjust bias currents in real-time. This closed-loop control ensures that delay variations are compensated dynamically, improving delay consistency without significantly increasing circuit complexity
2Reliability
If delay locked loop with external clock frequency adjustment is used, then delay consistency across process corners is improved, but the device complexity and external dependencies increase
Solution Approach 1:
The patent extracts and eliminates the dependency on external clock frequency adjustments by implementing an autonomous process corner detection and compensation mechanism. The delay line uses internal process monitoring and bias adjustment, removing the need for external clock control while maintaining delay consistency
Solution Approach 2:
The delay line circuit performs self-adjustment by continuously monitoring its own process conditions through integrated monitor transistors and automatically adjusting its bias currents. This self-service mechanism eliminates the need for external control systems, reducing overall system complexity while maintaining reliable delay consistency
Data Source
AI summary
An integrated circuit that equalizes delay across process corners. A delay equalizer circuit is used to adjust and maintain a relatively constant delay across different process corners. The delay equalizer circuit includes a process monitor and a delay compensator circuit coupled to the process monitor. The process monitor may output a compensating bias voltage for a pMOS transistor and a compensating bias voltage for an nMOS transistor. The compensating bias voltages may be used to regulate and maintain a relatively constant delay through the delay compensator circuit across varying process corners.