Process Data Receiver Clock Synchronization Elimination
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Solution Overview
Problem
Existing methods for transmitting process data in automated systems are costly and inefficient, particularly when high data transmission rates are required, as they often necessitate complex and expensive Phase Locked Loops (PLL) or oversampling, which are not feasible for large-scale, inexpensive implementations.
Innovation Solution
A method that uses oversampling to generate a serial receiver data stream with multiple samples per data symbol, allowing the process data receiver to select equidistant samples without a synchronized clock signal, thereby eliminating the need for a PLL and enabling cost-effective implementation with parallel data paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If Phase Locked Loops (PLL) are used to synchronize clock signals for high data transmission rates, then data transmission speed is improved, but device complexity and cost increase significantly
Solution Approach 1:
The patent extracts and eliminates the PLL component from the receiver design. Instead of using a PLL to generate a synchronized clock signal, the system uses a simplified approach where the receiver samples the incoming data stream at multiple points and selects the optimal sample points through digital processing, thereby removing the complex analog clock synchronization circuitry while maintaining high data transmission rates
Solution Approach 2:
The patent replaces the mechanical/analog PLL clock synchronization system with a digital sampling and selection system. The receiver uses multiple parallel sampling paths that operate at different phases, and through digital logic selects the correct data values from these samples, substituting the analog PLL mechanism with a digital equivalent that achieves the same synchronization function with reduced complexity
2Speed
If oversampling is used to achieve high data transmission rates, then data transmission speed is improved, but the requirement for super-fast circuits and high clock frequencies increases cost and complexity
Solution Approach 1:
The patent segments the single high-speed sampling operation into multiple lower-speed sampling operations performed in parallel. Instead of one super-fast circuit sampling at the optimal point, the system uses multiple circuits sampling at different phases, then selects the correct samples through digital logic. This segmentation allows each individual sampling circuit to operate at lower, more affordable clock frequencies while achieving the same effective data transmission rate
Solution Approach 2:
The patent transitions from a single-dimensional approach (one high-frequency clock) to a multi-dimensional approach (multiple lower-frequency clocks at different phases). By introducing the phase dimension, the system can achieve high effective sampling rates through parallel processing of multiple lower-frequency sampling streams, avoiding the need for super-fast single-frequency circuits
3Reliability
If synchronized clock signals are required for data reception, then data transmission reliability is improved, but the need for complex clock distribution systems increases device complexity
Solution Approach 1:
The patent implements a self-service approach where the receiver autonomously determines the optimal sampling points without requiring an external synchronized clock signal from the transmitter. The receiver uses its own local oscillators to generate multiple phase-shifted sampling clocks, samples the incoming data at these different phases, and selects the correct samples based on detected transition points. This eliminates the need for complex bidirectional clock synchronization while maintaining data reliability
Solution Approach 2:
The patent applies preliminary action by having the receiver pre-generate multiple phase-shifted sampling clocks before data reception begins. These pre-synchronized (to each other, not to the transmitter) clock signals are ready to sample the incoming data stream at different phases, allowing the receiver to adapt to the transmitter's timing without requiring the transmitter to provide a reference clock signal
Data Source
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AI summary
A process data transmitter transmits current process data at defined recurring intervals of time in the form of a serial transmission data stream (66) having a multiplicity of data symbols (68) at a defined symbol rate. A process data receiver samples the serial transmission data stream (66) at a sampling rate which is higher than the symbol rate by a defined factor in order to generate a serial receiver data stream (70) having a multiplicity of samples (72) for each data symbol (68). The process data receiver divides the serial receiver data stream (70) into data packets (86), each of which has a defined first number of samples (72). The process data receiver selects a defined second number of samples (72') from the respective data packets (86). The second number is smaller than the first number by the defined factor and the samples (72') selected from each data packet (86) are equidistant to one another. The process data receiver processes the selected samples (72') as received process data.