Processing Array Bit-Line Logic for Single-Cycle Full Adders
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Solution Overview
Problem
Current memory cells, such as SRAM cells, cannot perform certain logic functions like exclusive OR (XOR) operations efficiently, and full adder calculations typically require 4 clock cycles, whereas performing these operations in a single clock cycle is desirable for improved computational efficiency, especially in big data operations and machine learning applications.
Innovation Solution
A CMOS implemented memory cell and processing array with dual-port AND cells and 3-port SRAM complementary XOR cells that enable two logic computations per clock cycle, allowing for full adder operations in a single clock cycle by utilizing split read bit lines and advanced bit line read/write logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional SRAM cells are used for computation, then basic Boolean operations (AND, OR, NAND, NOR) can be performed, but certain logic functions like XOR cannot be performed efficiently
Solution Approach 1:
The patent implements a multi-functional memory cell that can perform both basic Boolean operations (AND, OR, NAND, NOR) and XOR operations, as well as full adder calculations. The cell achieves this versatility through configurable word lines and bit line read/write logic that enable different computational modes without requiring separate specialized cells for each function.
2Productivity
If conventional full adder circuitry is used, then floating point calculations can be performed, but the operation requires 4 clock cycles
Solution Approach 1:
The patent performs preliminary actions by pre-charging bit lines and preparing logic states before the actual computation cycle. The dual-port AND cell structure pre-positions data in both true and complement forms, enabling the full adder operation to complete in a single clock cycle rather than requiring multiple sequential cycles for data preparation and computation.
Solution Approach 2:
The patent segments the computation process into parallel operations within a single clock cycle by using split read bit lines and dual-port cell architecture. This segmentation allows simultaneous evaluation of multiple logic conditions (Ain, Bin, Cin inputs) and parallel generation of sum and carry outputs, eliminating the sequential timing requirements of conventional full adders.
3Productivity
If memory arrays are used for in-memory computation, then bandwidth bottlenecks are eliminated, but the memory cells must perform complex logic functions
Solution Approach 1:
The patent merges storage and computation functions into a unified memory cell structure. The dual-port AND cell combines storage elements with logic computation capabilities, allowing data to be stored and processed in the same location. This merging eliminates the need for separate memory and computation units, thereby eliminating bandwidth bottlenecks while maintaining practical cell complexity through shared circuitry.
Data Source
AI summary
A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.