Processing Array SRAM Logic for Single-Cycle Full Adder
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Solution Overview
Problem
Current memory cells, such as SRAM cells, cannot perform certain logic functions like exclusive OR (XOR) operations efficiently, and full adder operations typically require 4 clock cycles, which is undesirable for fast computations.
Innovation Solution
A CMOS implemented memory cell and processing array that enables full adder operations in a single clock cycle using dual-port AND cells and 3-port SRAM complementary XOR cells, allowing for faster Boolean operations and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional SRAM cells are used for computation, then basic Boolean operations (AND, OR, NAND, NOR) can be performed, but certain logic functions like XOR cannot be performed efficiently
Solution Approach 1:
The patent implements universal logic functionality by integrating both AND cell functionality and XOR functionality into the same memory cell structure. The 3-port SRAM cell can perform AND operations through its basic dual-port functionality while also performing XOR operations through selective write mode, eliminating the need for separate specialized cells for different logic functions.
2Speed
If conventional full adder circuitry is used, then floating point calculations can be performed, but the operation requires 4 clock cycles which slows down computation
Solution Approach 1:
The patent performs preliminary actions by pre-charging bit lines and pre-positioning data in memory cells before the actual full adder operation. The selective write mode is prepared in advance, and input operands are loaded into the memory array beforehand, enabling the full adder operation to complete in a single clock cycle rather than requiring multiple sequential cycles.
Solution Approach 2:
The patent maintains continuous useful action throughout the computation process by overlapping memory access operations with arithmetic operations. The dual-port capability allows simultaneous read and write operations, and the selective write mode enables continuous data transformation without idle clock cycles, achieving single-cycle full adder operation.
3Productivity
If memory arrays are used for in-memory computation, then bandwidth bottleneck is eliminated, but the memory cells must perform both storage and computation functions
Solution Approach 1:
The patent achieves multi-functionality by designing the memory cell to simultaneously serve as both a storage element and a computation element. The 3-port SRAM cell structure allows the same physical cell to store data and perform logic operations (AND, XOR) and arithmetic operations (full adder), eliminating the need for separate storage and computation hardware.
Solution Approach 2:
The memory cells perform self-service computation by utilizing their inherent read and write capabilities to execute logic and arithmetic operations without requiring external processing assistance. The selective write mode enables the cell to automatically perform XOR operations on stored data, and the full adder operation is self-contained within the memory array, eliminating the need for separate CPU intervention.
Data Source
AI summary
A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.