Specialized Processing Block Floating-Point Multiplier Subnormal Support

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Solution Overview

Problem

Specialized processing blocks in programmable logic devices (PLDs) lack support for floating-point operations, particularly for subnormal numbers, requiring additional circuitry outside the block, which is slower and less efficient.

Innovation Solution

Incorporating a modified adder within the specialized processing block to handle subnormal operations, allowing it to operate on the output of a multiplier and generate control signals for completing subnormal multiplication operations, thereby eliminating the need for general-purpose logic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If floating-point operations with subnormal numbers are implemented outside the specialized processing block using general-purpose programmable logic, then the specialized processing block maintains its simplicity and speed for standard operations, but the overall system performance deteriorates due to the slower general-purpose logic and increased latency

Engineering Contradiction:

Improveprocessing speedVSAvoidcircuitry complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the subnormal operation completion functionality into the specialized processing block by incorporating an adder that can operate in both normal and subnormal modes. This integration allows the block to handle all floating-point operations internally without external logic, eliminating the performance penalty of inter-block communication while maintaining the specialized block's architectural simplicity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The adder within the specialized processing block is designed with multi-functionality to handle both normal floating-point addition and the special case of completing subnormal operations. By making the adder universal, the block can accommodate subnormal number support without requiring separate dedicated circuitry, thus avoiding increased complexity while achieving full floating-point capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If additional circuitry is added outside the specialized processing block to handle subnormal operations, then IEEE754 floating-point compliance is achieved, but the processing latency increases and valuable general-purpose logic resources are consumed

Engineering Contradiction:

Improvefloating-point complianceVSAvoidprocessing latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

3Productivity

If the adder is borrowed to handle subnormal operations within the specialized processing block, then subnormal number support is achieved without external logic, but the adder becomes unavailable for other operations

Engineering Contradiction:

Improvesubnormal operation efficiencyVSAvoidadder availability

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The adder is designed with dynamic operational modes that allow it to adapt between normal addition operations and subnormal operation completion based on control signals. This dynamic capability enables the same hardware resource to serve multiple purposes at different times, resolving the conflict between dedicated subnormal support and general adder functionality.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The adder's operation parameters are changed based on control signals that indicate whether a subnormal operation is in progress. By modifying operational parameters (such as operand selection, result handling, and timing) rather than requiring separate hardware, the system achieves subnormal support without permanently sacrificing adder availability for other operations.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8996600B1Specialized processing block for implementing floating-point multiplier with subnormal operation support

Publication Date: 2015.03.31 ALTERA CORP

AI summary

The functions available in a specialized processing block of a programmable device include floating-point operations, including support within the specialized processing block for subnormal operations. This is accomplished, in part, by borrowing an adder in the specialized processing block and using the adder to operate on output of a multiplier or other operator to compete a subnormal operation. Although the adder becomes unavailable to serve as an adder, the need to complete the operation in slower, more valuable general purpose logic is avoided. The adder and the other operator need not necessarily be located together in a specialized processing block.