Processing Chip Pin Sharing via Transmission Gate Module
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Solution Overview
Problem
The existing chip systems require additional pins for programming and testing, which increases the area and disposition costs due to the need for specific pins for these functions.
Innovation Solution
A chip system with a processing chip that includes I/O pads, memory access pads, an I/O controller, a memory controller, and a transmission gate module, allowing for shared pins to perform programming and testing by enabling the transmission gate module under program or test modes, reducing the need for specific pins in the package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional pins are disposed in the package for programming and testing, then programming and testing functions can be performed, but the area cost and disposition cost of the chip system increase
Solution Approach 1:
The patent applies multi-functionality by enabling the I/O pins to serve dual purposes: general I/O operations during normal operation mode, and programming/testing operations when the transmission gate module is enabled. This allows the same physical pins to be reused for different functions at different times, eliminating the need for separate dedicated programming and testing pins, thereby reducing the overall pin count and chip system area cost
2Adaptability or versatility
If additional pins are disposed in the package for programming and testing, then programming and testing functions can be performed, but the disposition cost of the chip system increases
Solution Approach 1:
The patent reduces disposition cost by designing a universal pin structure where the I/O pins can be configured for different functions through software control of the transmission gate module, rather than requiring separate physical pins for each function. This universal design simplifies the manufacturing process and reduces the complexity of pin disposition planning and cost
3Quantity of substance
If the transmission gate module is enabled to share pins for programming and testing, then the need for additional pins is reduced, but the complexity of the processing chip increases
Solution Approach 1:
The transmission gate module acts as an intermediary component that enables shared use of I/O pins for multiple functions. It serves as a switching mechanism that routes signals appropriately based on the operational mode, allowing the system to reduce pin count while managing the added control logic complexity through a dedicated intermediary module
Data Source
AI summary
A chip system including I/O pins, a memory chip and a processing chip is provided. The processing chip includes I/O pads, memory access pads, a processor, an I/O controller, a memory controller and a transmission gate module. Under an operation mode, the I/O controller allows the processor to communicate with an external circuit device through the I/O controller, the I/O pads and the I/O pins. Under the operation mode, the memory controller allows the processor to access the memory chip through the memory controller and the memory access pads. The transmission gate module is enabled during a program mode or a test mode to allow the external circuit device to perform programming or testing on the memory chip through the I/O pins, the I/O pads, the transmission gate module and the memory access pads.