Processing Circuit Array for Flexible AI Computing

The patent divides the processing circuit into multiple processing circuit sub-arrays that can be independently configured and controlled. Each sub-array can be dynamically assigned to different operations based on the computing instruction, enabling flexible adaptation to various computational tasks while maintaining high processing performance through parallel execution.

The patent implements dynamic configuration of the processing circuit array where sub-arrays can be reconfigured based on operational requirements. The system can dynamically adjust the number of active sub-arrays, their arrangement, and their assigned operations to optimize both flexibility and processing performance for different computational workloads.

The patent merges multiple operations into a single computing instruction by parsing the instruction into multiple operation instructions that are executed in parallel across different processing circuit sub-arrays. This consolidation reduces the number of separate instructions needed, decreases on-chip I/O data throughput requirements, and improves execution efficiency through simultaneous operation execution.

The patent enables continuous execution of multiple operations through parallel processing circuits that operate simultaneously. By distributing operations across multiple sub-arrays that work in parallel, the system maintains continuous productive action without idle waiting periods, thereby improving execution efficiency while reducing the cumulative data throughput burden compared to sequential instruction execution.

The patent segments the computing task across multiple processing circuit sub-arrays that can execute operations in parallel. This segmentation enables faster execution speed by performing multiple operations simultaneously rather than sequentially, while power consumption is optimized by activating only the necessary number of sub-arrays for each specific computing task, avoiding the energy waste of keeping all circuits active.

The patent applies partial action by activating only the required number of processing circuit sub-arrays based on the complexity and requirements of the computing instruction. Instead of running all possible operations at full capacity, the system dynamically adjusts the level of computational action to match the actual task requirements, thereby achieving fast execution speeds while optimizing power consumption to avoid excessive energy usage.