Processing Circuit Phase Control for Radio Noise Reduction
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Solution Overview
Problem
Radio communication devices are sensitive to noise, leading to degradation in reception sensitivity due to uncertain phase relationships between clock signals and noise-induced harmonic noise from delta-sigma modulation, analog-to-digital conversion, and demodulation processes.
Innovation Solution
A processing circuit with a frequency dividing and delay circuit generates a clock signal with a phase difference, and a control circuit produces a conversion trigger signal to synchronize analog-to-digital conversion and demodulation, allowing for arbitrary phase settings between clock signals and conversion trigger signals, reducing noise and improving reception sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are generated with fixed phase relationships for analog-to-digital conversion and demodulation, then processing simplicity is maintained, but noise interference increases and reception sensitivity degrades
Solution Approach 1:
The patent implements dynamic phase adjustment of clock signals by introducing a phase adjustment unit that can vary the phase of the second clock signal relative to the first clock signal. This allows the system to adaptively optimize the phase relationship between clock signals and conversion trigger signals to minimize harmonic noise and improve reception sensitivity, rather than using fixed phase relationships.
Solution Approach 2:
The patent changes the phase parameter of clock signals to resolve the contradiction. By adjusting the phase of the second clock signal generated by the frequency dividing circuit, the system can optimize the timing relationship between sampling operations and processing operations, thereby reducing noise interference while maintaining manageable system complexity through controlled parameter variation.
2Object-affected harmful factors
If phase relationships between clock signals are arbitrarily set to minimize noise, then reception sensitivity improves, but system complexity increases
Solution Approach 1:
The patent introduces a phase adjustment unit as an intermediary component between the frequency dividing circuit and the processing circuits. This intermediary specifically manages the phase relationship between clock signals, isolating the complexity of phase control to a dedicated module while keeping the rest of the system relatively simple. The conversion trigger signal generation unit also acts as an intermediary to coordinate the timing between different operations.
Solution Approach 2:
The patent segments the clock signal generation and phase control functions into separate modules: a frequency dividing circuit for generating the second clock signal, a phase adjustment unit for modifying its phase, and a conversion trigger signal generation unit for coordinating operations. This segmentation allows each module to handle a specific aspect of phase control, reducing overall system complexity while achieving noise minimization.
3Reliability
If sampling and processing operations are synchronized with fixed timing, then operational simplicity is maintained, but harmonic noise increases and reception performance degrades
Solution Approach 1:
The patent implements dynamic timing adjustment by making the phase of the second clock signal variable rather than fixed. The phase adjustment unit enables the system to dynamically optimize the timing relationship between sampling operations (triggered by the first clock signal) and processing operations (triggered by the second clock signal), allowing the system to adapt to different operating conditions and minimize harmonic noise while maintaining operational effectiveness.
Data Source
AI summary
A processing circuit includes: a clock generating circuit configured to generate, based on a reference clock signal and a frequency division ratio, a first clock signal; a frequency dividing and delay circuit configured to generate a second clock signal to have a first phase difference with the reference clock signal by dividing the frequency of the first clock signal and delaying the first clock signal based on a phase shift set signal and the frequency division ratio; an analog-to-digital converter circuit configured to convert an analog signal into a digital signal based on the first clock signal and a conversion trigger signal indicating a sampling period and a conversion period; and a control circuit configured to generate the conversion trigger signal to have the same cycle as the second clock signal based on the frequency division ratio and the first clock signal.