Processing Circuit Pipeline for Sequential Data Performance

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Solution Overview

Problem

Processing circuits experience performance degradation when processing one piece of data ends and then another begins, compared to parallel processing of multiple data sets.

Innovation Solution

A processing circuit design where each calculation circuit is sequentially connected with multiple data holding units and a common data calculation unit, allowing the calculation result of one piece of data to be input to the next stage while processing another piece of data, enabling pipeline processing synchronized with a clock.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If processing is performed sequentially one piece of data at a time, then the processing circuit structure is simple, but processing performance deteriorates

Engineering Contradiction:
Improveprocessing performanceVSAvoidprocessing circuit structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The processing circuit is divided into multiple calculation circuits (first calculation circuit, second calculation circuit, etc.), each capable of independently processing different pieces of data. This segmentation allows parallel processing of multiple data items simultaneously, improving productivity while maintaining manageable circuit complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a pipeline structure where calculation circuits are arranged in sequence with data holding units between them, creating a multi-stage processing dimension. This allows data to flow through multiple processing stages simultaneously, enabling overlap between different data items being processed at different stages

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If processing of one data item completes before starting the next, then data processing is straightforward, but processing performance drops compared to parallel processing

Engineering Contradiction:
Improveprocessing performanceVSAvoidprocessing time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The first calculation circuit performs preliminary processing on multiple data items simultaneously before the data reaches subsequent calculation circuits. This preliminary action prepares data in advance for later stages, enabling overlapping of processing operations and reducing total processing time

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Multiple calculation circuits operate continuously and in parallel on different data items without idle time between operations. The pipeline structure ensures that while one circuit is processing current data, other circuits are simultaneously processing previous data items, maintaining continuous useful action throughout the processing timeline

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS20240248510A1Processing circuit and non-transitory computer readable medium storing processing program
Publication Date: 2024.07.25 FUJIFILM BUSINESS INNOVATION CORP
  • US20240248510A1 patent drawing
  • US20240248510A1 patent drawing
  • US20240248510A1 patent drawing

AI summary

A processing circuit includes a calculation circuit that is sequentially connected, the calculation circuit including plural data holding units that hold plural pieces of data for each piece of data and one data calculation unit that is common to each of the data holding units and performs a predetermined calculation on each piece of data held in the data holding unit, in which a calculation result of the calculation circuit of a preceding stage is input to the data holding unit in the calculation circuit of a succeeding stage associated with data which is a calculation target in the calculation circuit of the preceding stage, and while the calculation circuit of the preceding stage performs the predetermined calculation on any piece of data, the calculation circuit of the succeeding stage performs the predetermined calculation on a calculation result obtained from another piece of data different from the data, which is the calculation target in the calculation circuit of the preceding stage, to perform the predetermined calculation on each piece of data.