Processing Circuit Segmented Multipliers for Cryptography
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing cryptographic processing circuits are inefficient in performing integer multiplications, particularly in asymmetric cryptography and post-quantum cryptography, due to high power consumption and area requirements, which hinders processing speed.
Innovation Solution
A processing circuit architecture that separates operands into most significant and least significant bit portions, allowing for efficient multiplication operations through three multipliers and an output circuit that calculates the final product by combining the results with correction terms, enabling both full operand and SIMD modes to optimize area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional multiplication circuits are used for cryptographic processing, then processing speed can be maintained, but chip area and power consumption increase significantly
Solution Approach 1:
The multiplication operation is segmented into three separate multiplication circuits that compute partial products of different bit ranges (least significant bits, middle bits, and most significant bits). These partial results are then combined through addition circuits to produce the final product. This segmentation allows each multiplication circuit to be optimized for specific bit ranges, reducing overall area while maintaining processing speed.
Solution Approach 2:
The patent transforms the traditional single multiplication operation into a multi-dimensional computation space by introducing parallel partial product calculations. Instead of one large multiplication circuit, the design uses multiple smaller multiplication circuits operating in parallel, with results combined through addition. This dimensional transformation from sequential to parallel processing reduces area while preserving throughput.
2Productivity
If traditional multiplication circuits are used for cryptographic processing, then processing speed can be maintained, but power consumption increases significantly
Solution Approach 1:
The power consumption is reduced by segmenting the multiplication into three separate circuits that handle different bit ranges. Each segment processes only a portion of the total computation, thereby reducing the instantaneous power draw of any single circuit while maintaining overall processing speed through parallel operation.
Solution Approach 2:
The patent applies partial action by having three multiplication circuits compute only the necessary partial products required for the final result, rather than one circuit computing everything. This partial computation approach, followed by combination through addition, reduces total power consumption while achieving the same processing throughput.
3Area of stationary object
If three multiplier architecture is used, then chip area and power consumption are reduced, but circuit complexity increases
Solution Approach 1:
While segmentation into three multipliers increases the number of components, each individual multiplier is simpler than a single full-size multiplier would be. The segmentation allows for modular design and reuse of identical circuit blocks, which can simplify manufacturing and testing despite the increased component count.
Solution Approach 2:
The patent merges the results from three separate multiplication circuits through addition circuits to produce the final product. This merging process consolidates the output of multiple simple operations into a single complex result, managing circuit complexity by organizing computations in a structured hierarchy rather than using one monolithic complex circuit.
4Use of energy by stationary object
If three multiplier architecture is used, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The device uses partial action by having three multiplication circuits compute only the necessary partial products, reducing total power consumption. The complexity is managed by organizing these partial computations in a systematic way that can be efficiently implemented in hardware, with clear separation of computation stages.
Data Source
AI summary
A processing circuit including a first multiplier to multiply least significant portions of a first and a second operand, a second multiplier to multiply a sum of a most and the least significant portion of the first operand with the sum of a most and the least significant portion of the second operand and the least significant portion of the second operand, a third multiplier to multiply the most significant portions of the first and the second operand and an output circuit to determine an output sum including the result of the first multiplier, the result of the third multiplier times two to the power of two times the bit number of the least significant portions, and, if enabled, the result of the second multiplier minus the results of the first and the third multiplier, times two to the power of the bit number of the least significant portions.