Processing Cluster with Global Load Store for Parallel Execution

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Solution Overview

Problem

Current processing clusters face inefficiencies in parallel execution due to synchronization overhead, limited re-use, and poor adaptability, making it difficult to effectively utilize multiple cores for complex algorithms like video processing, which requires efficient data interaction and synchronization between parallel programs.

Innovation Solution

A method and apparatus that involve a system programming tool to generate hosted application code, allocate compute and memory resources, and create data structures within a processing cluster, enabling efficient parallel processing by resolving data dependencies through hardware and using a parallel processing architecture with global load store circuitry and shared function memory, allowing for efficient data communication and synchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If synchronization mechanisms are used to coordinate parallel execution, then reliability of data interaction is improved, but overhead and execution time increase

Engineering Contradiction:
Improvedata interaction reliabilityVSAvoidsynchronization overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the synchronization function from traditional software-based mechanisms and implements it through dedicated hardware circuitry within the processing cluster. This extraction enables synchronization to occur at the hardware level, significantly reducing the time overhead while maintaining reliability of data interaction between parallel execution units.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces intermediary hardware structures including shared memory circuits and interconnect fabric that mediate data exchange between processing elements. These intermediaries provide standardized interfaces and automatic synchronization capabilities, eliminating the need for complex software synchronization protocols and reducing execution overhead.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If general-purpose processor features are included to provide flexibility, then adaptability is improved, but area efficiency deteriorates

Engineering Contradiction:
Improveprocessor flexibilityVSAvoidchip area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent segments the processing cluster into multiple independent processing elements that can be selectively instantiated and configured. Each processing element is a self-contained unit with its own execution resources, allowing the system to activate only the necessary number and type of elements for a given application, thereby optimizing area usage while maintaining flexibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic configuration capabilities where the processing cluster can be reconfigured at runtime based on application requirements. Processing elements can be dynamically activated, deactivated, or reconfigured to handle different workloads, enabling the same hardware to adapt to varying computational demands without permanently allocating resources for all possible scenarios.

Inventive Principle:
Principle #15Dynamics

3Productivity

If more processing elements are added to increase parallelism, then productivity is improved, but device complexity increases

Engineering Contradiction:
Improveparallel processing throughputVSAvoidcluster architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent designs processing elements with universal interfaces and standardized communication protocols that enable them to function in various configurations. Each processing element can operate independently or in combination with others, and the same interconnect fabric supports multiple communication patterns. This universality allows scalability without proportionally increasing system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges multiple processing elements into a unified processing cluster with shared resources including memory circuits, interconnect fabric, and control logic. This merging approach allows parallel execution while consolidating common functions, thereby increasing productivity without linearly increasing overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

4Use of energy by moving object

If hardware resources are dedicated to specific algorithms, then energy efficiency is improved, but re-use capability deteriorates

Engineering Contradiction:
Improvealgorithm execution energyVSAvoidalgorithm re-use
Core Design Contradiction:
Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamically reconfigurable processing elements that can change their operational mode and configuration based on the current algorithm being executed. This dynamic adaptation allows the same hardware resources to be optimized for different algorithms sequentially, maintaining energy efficiency for each specific algorithm while preserving re-use capability across multiple applications.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent utilizes parameter changes in the processing elements to adapt to different algorithms. By modifying operational parameters such as data formats, computation modes, and resource allocation settings, the same hardware can efficiently execute diverse algorithms without requiring dedicated hardware for each one, thus maintaining both energy efficiency and re-usability.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9552206B2Integrated circuit with control node circuitry and processing circuitry
Publication Date: 2017.01.24 TEXAS INSTR DEUTLAND GMBH
  • US9552206B2 patent drawing
  • US9552206B2 patent drawing
  • US9552206B2 patent drawing

AI summary

Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system is provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured “on the fly” to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user. Generally, a control node connected to the address and data leads of a host processor uses messages to control the processing of data in a processing cluster. The cluster includes nodes of parallel processors, shared function memory, a global load/store, and hardware accelerators all connected to the control node by message busses. A crossbar data interconnect routes data to the cluster circuits separate from the message busses.