Processing Core With Integrated CBA NAND and HBM Memory

Solution Overview

Problem

Conventional processing cores, including GPUs and AI processors, face inadequate memory capacity and bandwidth requirements, with non-volatile memories offering low bandwidth and high power consumption, while volatile memories provide insufficient capacity.

Innovation Solution

Integrate a processor directly onto a high-bandwidth, high-capacity non-volatile memory tile, such as a CBA memory tile, with passthrough zones for direct data transfer and reduced parasitics, using CMOS bonded array technology, and affix it to an interposer with HBM stacks for enhanced data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If non-volatile memories (NAND dies) are used for large memory capacity, then memory capacity is improved, but bandwidth rate deteriorates and power requirements increase

Engineering Contradiction:

Improvememory capacityVSAvoidbandwidth rate

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The memory system is segmented into multiple types: non-volatile NAND memory for capacity, volatile DRAM for bandwidth, and SRAM for caching. Each segment serves a specific function to overcome the limitations of individual memory types.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from traditional 2D memory layouts to 3D stacked architectures, placing memory dies vertically above the processor. This dimensional change enables higher capacity and bandwidth by increasing the number of memory layers without expanding the footprint.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If non-volatile memories (NAND dies) are used for large memory capacity, then memory capacity is improved, but power requirements worsen

Engineering Contradiction:

Improvememory capacityVSAvoidpower requirements

Core Design Contradiction:

Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The memory system is segmented into multiple types: non-volatile NAND memory for capacity, volatile DRAM for bandwidth, and SRAM for caching. Each segment serves a specific function to overcome the limitations of individual memory types.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different memory regions have different characteristics optimized for their specific functions. NAND memory provides high-capacity non-volatile storage, DRAM provides high-speed volatile storage, and SRAM provides ultra-fast caching, with each region having tailored properties for its purpose.

Inventive Principle:

Principle #3Local quality

3Productivity

If volatile memories (DRAM dies) are used for high bandwidth, then bandwidth is improved, but memory capacity deteriorates

Engineering Contradiction:

ImprovebandwidthVSAvoidmemory capacity

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The memory system is segmented into multiple types: non-volatile NAND memory for capacity, volatile DRAM for bandwidth, and SRAM for caching. Each segment serves a specific function to overcome the limitations of individual memory types.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The memory architecture implements a nested hierarchy where SRAM caches are embedded within DRAM structures, which are in turn integrated with NAND memory stacks. This nested arrangement allows fast memory to be embedded within slower, higher-capacity memory systems.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS12430274B2Processing core including integrated high capacity high bandwidth storage memory

Publication Date: 2025.09.30 SANDISK TECHNOLOGIES LLC

AI summary

A processing core includes a multi-core processor integrated directly onto a high bandwidth, high-capacity non-volatile memory. The processor may for example be a large graphics processing unit (GPU) or artificial intelligence (AI) processor. The non-volatile memory may comprise a CBA (CMOS bonded to array) memory tile having a single large NAND memory tile coupled together with a CMOS logic circuit tile. The integrated processor and CBA memory tile may be affixed to an interposer. The processing core may further include stacks of high bandwidth memory (HBM) semiconductor dies affixed to the interposer around one or more sides of the processor and CBA memory tile.