Processing-in-Memory Data Evaluation Logic
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Solution Overview
Problem
Conventional computer architectures face increased data transfer latency and reduced performance due to the distance between remote processing units and memory, while representing data with fewer bits can lead to suboptimal results, and using too many bits wastes resources.
Innovation Solution
A processing-in-memory component evaluates the number of bits required to represent data stored in memory locations independently of host processor traffic, performing data evaluation logic to determine the optimal bit representation, thereby reducing unnecessary processing and memory bus traffic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred from memory to remote processing unit for evaluation, then processing can be performed, but data transfer latency increases and performance decreases
Solution Approach 1:
The patent combines the processing unit with the memory structure to form a processing-in-memory component. This merging eliminates the need for separate data transfer between memory and remote processing unit, allowing data evaluation to occur directly within the memory structure and thereby reducing data transfer latency while maintaining processing capability.
2Productivity
If data is represented with fewer bits, then processing resources and memory bandwidth are reduced, but representation accuracy decreases
Solution Approach 1:
The processing-in-memory component performs preliminary evaluation of data representation requirements directly in memory before data is transferred to the host processor. By evaluating the actual bit requirements of the data in place, the system can determine the optimal bit representation needed, avoiding both over-provisioning and under-provisioning of bits, thus balancing processing efficiency with representation accuracy.
3Productivity
If data is transferred to host processor for processing, then computation can be performed, but memory bus traffic increases and host processor cycles are consumed
Solution Approach 1:
The patent extracts the data evaluation function from the host processor and implements it within the processing-in-memory component. This extraction allows the evaluation operations to be performed locally in memory without requiring data to be transferred to the host processor, thereby reducing memory bus traffic and freeing up host processor cycles while maintaining computation capability.
Data Source
AI summary
Data evaluation using processing-in-memory is described. In accordance with the described techniques, data evaluation logic is loaded into a processing-in-memory component. The processing-in-memory component executes the data evaluation logic to evaluate a minimum number of bits required to retrieve data from, or store data to, at least one memory location. A result is output indicating the number of bits required to represent data at the at least one memory location based on the evaluation.