Processing-in-Memory Shared I/O Line Architecture
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Solution Overview
Problem
Current memory devices face inefficiencies in processing performance and power consumption due to the need for external communication between processing resources and memory arrays, which can be improved by integrating processing capabilities directly within the memory device.
Innovation Solution
The implementation of a processing-in-memory (PIM) device with a shared input/output (I/O) line that couples sensing circuitry, including a sense amplifier and compute components, directly to the memory array, allowing for simultaneous performance of compute operations with read and write operations within the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is accessed via external bus between processing resources and memory array, then device complexity is reduced, but processing speed decreases and power consumption increases
Solution Approach 1:
The patent merges processing resources (functional units with ALU, FPU, combinatorial logic) directly with the memory array by implementing them on the same chip. This integration eliminates external bus communications, reducing both access time and power consumption while maintaining device functionality.
Solution Approach 2:
The patent introduces an on-chip buffer and sequencer as intermediaries between the memory array and functional units. These components manage data flow and operation sequencing internally, enabling fast processing without requiring external bus transactions.
2Use of energy by moving object
If processing resources are implemented externally to memory array, then ease of operation is improved, but power consumption increases
Solution Approach 1:
By combining memory array and processing resources on the same chip, the patent eliminates power-hungry external bus transactions. The integrated architecture performs compute operations directly on stored data, significantly reducing overall power consumption while maintaining operational simplicity through unified control.
3Productivity
If compute operations are performed sequentially outside memory, then device complexity is reduced, but productivity decreases
Solution Approach 1:
The patent combines multiple functional units (ALU, FPU, combinatorial logic) with the memory array on the same chip, enabling parallel compute operations. This integration allows multiple operations to execute simultaneously on different data sets, dramatically improving processing throughput.
Solution Approach 2:
The on-chip buffer pre-loads and sequences data before it reaches the functional units, and the result buffer immediately captures outputs. This preliminary preparation and immediate capture of data eliminate waiting time between operations, enhancing overall processing productivity.
Data Source
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AI summary
The present disclosure includes apparatuses and methods for compute in data path. An example apparatus includes an array of memory cells. Sensing circuitry is coupled to the array of memory cells. A shared input/output (I/O) line provides a data path associated with the array. The shared I/O line couples the sensing circuitry to a compute component in the data path of the shared I/O line.