Processing-in-Memory Device Shared I/O Lines Parallel Compute
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Solution Overview
Problem
Current memory systems face inefficiencies in processing performance and power consumption due to the need for external communication between processing resources and memory arrays, which can slow down operation cycles and increase energy use.
Innovation Solution
The implementation of a processing-in-memory (PIM) device with shared input/output (I/O) lines that allow for simultaneous compute operations directly within the data path of a memory array, using sensing circuitry and compute components to perform operations on data stored in memory cells without requiring data to be moved externally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If data is transferred externally between memory array and processing resources, then data access is achieved, but processing time increases and power consumption increases
Solution Approach 1:
The patent merges memory array and processing resources into a single integrated structure where processing elements are embedded within the memory array. This allows compute operations to be performed directly on data stored in memory cells, eliminating the need for external data transfer between separate memory and processing components, thereby reducing power consumption while maintaining or improving processing performance.
Solution Approach 2:
The patent introduces sensing circuitry as an intermediary component that enables direct interaction between memory cells and processing elements. The sensing circuitry reads data from memory cells and provides it to processing elements for compute operations, allowing data to be processed in-place without external transfer, thus reducing power consumption while enabling efficient data access.
2Speed
If data is transferred externally between memory array and processing resources, then data access is achieved, but operation cycle time increases
Solution Approach 1:
The patent merges memory array and processing resources into a single integrated structure where processing elements are embedded within the memory array. This allows compute operations to be performed directly on data stored in memory cells, eliminating the need for external data transfer between separate memory and processing components, thereby reducing processing time while maintaining or improving operation cycle speed.
Solution Approach 2:
The patent enables processing elements to perform compute operations on data immediately after it is read from memory cells by sensing circuitry, before the data would normally be transferred externally. This preliminary processing action occurs in-place within the memory array, reducing the overall operation cycle time by eliminating subsequent external data transfer steps.
3Ease of operation
If processing resources are implemented externally to memory array, then data processing is achieved, but communication overhead increases
Solution Approach 1:
The patent merges memory array and processing resources into a single integrated structure where processing elements are embedded within the memory array. This integration simplifies the system architecture by eliminating the need for complex external communication interfaces and data transfer protocols between separate memory and processing components, while maintaining ease of data access through the unified structure.
Data Source
AI summary
The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.