Processing-in-Memory Transaction Scheduling to Reduce Bus Traffic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional computer architectures suffer from increased data transfer latency and reduced memory bandwidth due to the distance between processing units and memory, leading to inefficiencies and increased power consumption, particularly in memory-intensive computations.
Innovation Solution
Implementing a memory controller with a scheduling module that manages processing-in-memory transactions, using a transaction header buffer to prioritize and arbitrate requests, avoiding conflicts, and sending acknowledgement or negative acknowledgement messages to hosts to manage transaction execution by PIM components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional computer architectures are used with processing units far from memory, then device complexity is reduced, but data transfer latency increases and memory bandwidth decreases
Solution Approach 1:
The patent embeds processing-in-memory components directly within the memory module, creating a nested structure where processing units are integrated into the memory hierarchy. This nesting eliminates the need for separate processing units and long data transfer paths, thereby reducing data transfer latency while maintaining manageable device complexity through modular integration.
Solution Approach 2:
The patent introduces a memory controller with a scheduling module as an intermediary between hosts and PIM components. This mediator manages transaction scheduling, arbitrates resource access, and coordinates operations between multiple hosts and PIM components, enabling efficient memory-level processing while managing the complexity of inter-component communication.
2Productivity
If multiple hosts access shared memory simultaneously, then productivity increases, but memory bus traffic increases and conflicts occur
Solution Approach 1:
The scheduling module performs preliminary actions by pre-scheduling transactions and pre-arbitrating resource access requests before actual memory operations occur. This advance scheduling organizes memory bus traffic patterns, reduces conflicts, and optimizes throughput while minimizing retransmissions and energy waste from conflict resolution.
Solution Approach 2:
The scheduling module implements feedback mechanisms by monitoring memory bus traffic, detecting conflicts, and dynamically adjusting transaction scheduling decisions. This feedback loop enables the system to optimize productivity by routing transactions efficiently while reducing power consumption through conflict avoidance and load balancing across multiple PIM components.
Data Source
AI summary
Scheduling processing-in-memory transactions is described. In accordance with the described techniques, a memory controller receives a transaction header from a host, where the transaction header describes a number of operations to be executed by a processing-in-memory component as part of performing the transaction. The memory controller adds the transaction header to a buffer and sends either an acknowledgement message or a negative acknowledgement message to the host, based on a current load of the processing-in-memory component. The acknowledgement message causes the host to send operations of the transaction for execution by the processing-in-memory component and the negative acknowledgement message causes the host to refrain from sending the operations of the transaction for execution by the processing-in-memory component.