Processing-In-Memory Verification to Reduce Memory Bus Traffic
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Solution Overview
Problem
Conventional memory testing methods using memory diagnostic software are disruptive, consume processing resources, increase memory bus traffic, and are inefficient for high-bandwidth memory or high-performance computing environments.
Innovation Solution
Implementing a processing-in-memory component within a memory module to execute memory testing logic, allowing for memory verification without causing additional traffic on the interconnect, thereby reducing contention and saving processing cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory diagnostic software is used to test memory, then memory verification is achieved, but processing resources are consumed and memory bus traffic increases
Solution Approach 1:
The memory module performs self-verification through an integrated verification unit that executes test patterns locally without requiring external processing resources. The verification unit is coupled to the memory cells and can autonomously write test data, read it back, and detect faults without involving the host processor or consuming system processing resources.
Solution Approach 2:
The verification function is extracted from the host processor and embedded directly into the memory module as a separate verification unit. This extraction allows memory testing to occur independently without interfering with host processor operations or consuming system processing resources.
2Reliability
If memory diagnostic software is used to test memory, then memory verification is achieved, but memory bus traffic and contention increase
Solution Approach 1:
The memory module performs self-verification through an integrated verification unit that executes test patterns locally without requiring external processing resources. The verification unit is coupled to the memory cells and can autonomously write test data, read it back, and detect faults without involving the host processor or consuming system processing resources.
Solution Approach 2:
The verification function is extracted from the host processor and embedded directly into the memory module as a separate verification unit. This extraction allows memory testing to occur independently without interfering with host processor operations or consuming system processing resources.
3Productivity
If remote processing units are used for data processing, then processing capability is provided, but data transfer latency increases
Solution Approach 1:
The verification unit is merged with the memory module, combining storage and verification functions into a single integrated component. This eliminates the need for separate data transfer between memory and processing units, thereby reducing latency while maintaining verification capability.
Solution Approach 2:
The verification function transitions from a remote processing operation to a local in-memory operation. By moving the verification capability into the memory dimension itself rather than keeping it separate in the processing dimension, the system achieves faster verification without compromising processing capability.
Data Source
AI summary
Memory verification using processing-in-memory is described. In accordance with the described techniques, memory testing logic is loaded into a processing-in-memory component. The processing-in-memory component executes the memory testing logic to test a memory. An indication is output of a detected fault in the memory based on testing the memory.