Processing-in-Sensor and In-Memory Computing Integration
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Solution Overview
Problem
Current image recognition systems using deep neural networks face inefficiencies in energy consumption and data processing due to independent processing of pixel arrays and in-memory data, with no effective system for integrating these for efficient communication and calculation.
Innovation Solution
A method and system integrating a processing-in-sensor unit and an in-memory computing unit, utilizing a bus unit with synchronizing, frame difference, bit-slicing, and encoding modules to convert and transmit data between units operating at different clock frequencies, reducing data excess and improving transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If pixel array and in-memory data are processed independently through Von Neumann model with data transfer to computing unit, then data processing can be performed, but energy consumption increases and processing efficiency decreases due to large amount of data transportation
Solution Approach 1:
The patent merges the pixel array unit and in-memory computing unit into a single integrated system that shares common memory resources. This integration eliminates the need for separate data transfers between independent units, reducing energy consumption while maintaining processing efficiency through unified memory access.
Solution Approach 2:
The patent introduces a memory management unit as an intermediary that coordinates access between the pixel array and in-memory computing unit. This mediator optimizes data flow and reduces redundant data transportation, thereby lowering energy consumption while preserving processing throughput.
2Productivity
If data is transferred between pixel array and computing unit through various carriers, then calculations can be performed, but transmission efficiency decreases due to lack of integration and synchronization mechanisms
Solution Approach 1:
The patent combines the pixel array and computing unit into an integrated architecture with shared memory, eliminating the need for complex external data carriers and transmission protocols. This merger simplifies the system while improving transmission efficiency through direct memory access.
Solution Approach 2:
The patent implements dynamic clock frequency adjustment and synchronized control signals that adapt to data transfer requirements. This dynamic synchronization mechanism optimizes transmission efficiency while managing system complexity through intelligent control rather than rigid architectural complexity.
3Adaptability or versatility
If different clock frequencies are used for processing-in-sensor unit and in-memory computing unit, then each unit can operate optimally, but coordination and data transmission between units becomes complex
Solution Approach 1:
The patent introduces a clock synchronization mechanism that acts as an intermediary between units operating at different frequencies. This mediator translates and coordinates timing signals, allowing each unit to maintain its optimal operating frequency while ensuring proper data coordination and transmission.
Solution Approach 2:
The patent employs dynamic parameter adjustment including clock frequency scaling and timing offset calibration to accommodate different operating frequencies. By changing temporal parameters dynamically, the system achieves operational flexibility while managing synchronization complexity through adaptive control.
Data Source
AI summary
A method for integrating a processing-in-sensor unit and an in-memory computing includes the following steps. A providing step is performed to transmit the first command signal and the initial data to the in-memory computing unit. A converting step is performed to drive the first command signal and the initial data to convert to a second command signal and a plurality of input data through a synchronizing module. A fetching step is performed to drive a frame difference module to receive the input data to fetch a plurality of difference data. A slicing step is performed to drive a bit-slicing module to receive the difference data and slice each of the difference data into a plurality of bit slices. A controlling step is performed to encode the difference address into a control signal, and the in-memory computing unit accesses each of the bit slices according to the control signal.