Processing Task Duplication for Low-Overhead Fault Detection

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Solution Overview

Problem

Safety-critical data processing systems face challenges in meeting stringent safety standards due to random hardware errors and transient events, leading to increased power and area consumption in redundancy methods like dual lockstep processors, which are not feasible in applications like advanced driver-assistance systems and autonomous vehicles.

Innovation Solution

A method and system that duplicates input tasks into first and second tasks, allocates separate memory blocks for read-write, read-only, and shared read-only data, and processes these tasks independently while comparing signatures to detect faults, reducing the need for additional processing units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dual lockstep processors are used to detect faults, then system reliability is improved, but chip area and power consumption double

Engineering Contradiction:
Improvefault detection capabilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the fault detection functionality into the existing processor pipeline by having processing elements process duplicate tasks and compare outputs within the same computational unit, rather than using separate redundant processors. This combining approach maintains fault detection while avoiding the area and power penalty of fully independent dual processors.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent uses task duplication where the same input task is copied and processed by the same processing element twice, with the outputs being compared for faults. This eliminates the need for physical hardware copying while still achieving the fault detection effect through computational redundancy.

Inventive Principle:
Principle #26Copying

2Reliability

If dual lockstep processors are used to detect faults, then system reliability is improved, but power consumption doubles

Engineering Contradiction:
Improvefault detection capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent combines fault detection with the primary processing function by using the same processing element to execute both task instances and perform the comparison, eliminating the need for separate power-consuming redundant hardware circuits.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

By copying the task logic rather than the physical processor, the system achieves computational redundancy without the proportional increase in power consumption that would result from duplicating the entire processor hardware.

Inventive Principle:
Principle #26Copying

3Reliability

If separate memory blocks are allocated for first and second tasks, then fault detection accuracy is improved, but memory usage increases

Engineering Contradiction:
Improvefault detection accuracyVSAvoidmemory usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies local quality by allocating separate memory blocks specifically for read-write data that needs to be independent between task instances, while allowing shared access to read-only data. This selective separation provides fault detection accuracy where needed without unnecessarily duplicating all memory resources.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent makes read-only memory blocks universally accessible to both task instances, allowing the same memory resources to serve multiple purposes and both tasks simultaneously, thereby reducing overall memory usage while maintaining fault detection capability through separate read-write memory allocation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250307061A1Processing Tasks in a Processing System
Publication Date: 2025.10.02 IMAGINATION TECH LTD
  • US20250307061A1 patent drawing
  • US20250307061A1 patent drawing
  • US20250307061A1 patent drawing

AI summary

A method of processing an input task in a processing system involves duplicating the input task so as to form a first task and a second task; allocating memory including a first block of memory configured to store read-write data to be accessed during the processing of the first task; a second block of memory configured to store a copy of the read-write data to be accessed during the processing of the second task; and a third block of memory configured to store read-only data to be accessed during the processing of both the first task and the second task; and processing the first task and the second task at processing logic of the processing system so as to, respectively, generate first and second outputs.