Processing Time Reduction Signaling for Wireless Latency

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Solution Overview

Problem

Current wireless communication systems face limitations in flexibility and efficiency, particularly in reducing packet data latency and round trip delay, which hinders improved communication capacity, speed, and responsiveness, especially for real-time applications and the emerging Tactile Internet.

Innovation Solution

The implementation of processing time reduction for legacy transmission timing interval (TTI) in wireless communication systems, allowing for flexible fallback to normal RTT communication, involves methods such as Radio Resource Control configuration, transport block size-dependent settings, and DCI format indications to adjust processing times for HARQ-ACK reporting and scheduling of PDSCH and PUSCH transmissions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If processing time reduction is implemented for legacy TTI, then user plane latency is reduced and communication speed is improved, but system complexity increases due to multiple configuration modes and fallback mechanisms

Engineering Contradiction:
Improveuser plane latencyVSAvoidsystem complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent implements dynamic processing time adjustment by introducing a processing time value k that can be configured differently based on transport block size. The system can switch between normal processing time (k=4) and reduced processing time (k<4) configurations, allowing flexible adaptation to different traffic conditions and device capabilities while maintaining backward compatibility with legacy systems

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the processing time parameter by introducing variable k values based on transport block size thresholds. When transport block size exceeds a threshold, reduced processing time (smaller k) is applied; otherwise, normal processing time (k=4) is used. This parameter change enables latency reduction for large packets while maintaining stability for smaller transmissions

Inventive Principle:
Principle #35Parameter changes

2Productivity

If processing time is reduced dynamically based on transport block size, then communication efficiency is improved, but device complexity increases due to additional configuration and determination logic

Engineering Contradiction:
Improvecommunication efficiencyVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies different processing time configurations to different transport block sizes. Large transport blocks (exceeding threshold) receive reduced processing time configuration for faster handling, while smaller transport blocks use normal processing time. This local quality approach optimizes efficiency for latency-sensitive large packet transmissions without unnecessarily complicating smaller packet handling

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements partial processing time reduction by applying reduced k values only when transport block size exceeds a configured threshold. This selective application provides efficiency improvement where needed (large packets requiring faster processing) while avoiding unnecessary complexity for smaller packets that can handle normal processing times

Inventive Principle:
Principle #16Partial or excessive action

3Adaptability or versatility

If flexible fallback to normal RTT communication is implemented, then adaptability is improved, but system complexity increases due to multiple operation modes

Engineering Contradiction:
ImproveadaptabilityVSAvoidsystem complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent creates a universal processing time configuration framework that supports both reduced processing time mode and normal RTT communication mode. The system can operate in either mode depending on configuration and traffic conditions, providing multi-functionality that enhances adaptability while maintaining a unified underlying architecture for both operation modes

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10595166B2Systems and methods for processing time reduction signaling
Publication Date: 2020.03.17 SHARP KK
  • US10595166B2 patent drawing
  • US10595166B2 patent drawing
  • US10595166B2 patent drawing

AI summary

A user equipment (UE) is described. The UE includes a processor and memory in electronic communication with the processor. Instructions stored in the memory are executable to receive a configuration message of processing time reduction from an evolved node B (eNB). The instructions are also executable to determine a processing time value k for a physical downlink shared channel (PDSCH) transmission. The instructions are further executable to receive the PDSCH in subframe n−k. The instructions are additionally executable to transmit hybrid automatic repeat request-acknowledgement (HARQ-ACK) in subframe n for the PDSCH transmission in subframe n−k.