Processing Unit Spiral Algorithm Convolution Hardware
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Solution Overview
Problem
Processing units that compute convolutions require multiple processing elements and discrete memories, leading to high chip area and energy consumption, especially in applications like image processing, AI, and machine learning, and existing systolic arrays with data setup logic blocks are also costly.
Innovation Solution
A processing unit employing an array of processing elements and a hardware-implemented spiral algorithm to compute convolutions, eliminating the need for a discrete data setup logic block by pre-loading activation values and using a spiral pattern to select weight values, allowing parallel multiply-accumulate operations in a low number of clock cycles independent of activation and weight values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processing elements with discrete memories are used to compute convolution, then the computation can be completed, but chip area consumption increases
Solution Approach 1:
The patent merges the memory function into the processing elements themselves. Each processing element in the array includes local storage to hold activation values, eliminating the need for separate discrete memories for each PE. This integration reduces overall chip area while maintaining the capability to perform convolution computations across multiple processing elements.
Solution Approach 2:
The processing elements are designed with multi-functionality, serving both as computation units and as storage units. The same processing element that performs multiply-accumulate operations also contains local memory to store activation values, thereby reducing the total number of memory components needed in the system and decreasing chip area consumption.
2Productivity
If multiple processing elements with discrete memories are used to compute convolution, then the computation can be completed, but energy consumption increases
Solution Approach 1:
By merging memory and processing functions into unified processing elements, the patent eliminates the need for frequent data transfers between separate memory components and processing units. This reduction in data movement significantly decreases energy consumption, as memory access and data transfer are among the most energy-intensive operations in computing systems.
Solution Approach 2:
The patent implements preliminary loading of activation values into the local storage of processing elements before the convolution computation begins. This pre-positioning of data ensures that processing elements have immediate access to required values during computation, eliminating the need for repeated energy-consuming memory accesses during the actual convolution operation.
3Ease of operation
If a data setup logic block is used to reorganize data in systolic arrays, then data inputs are in proper order for processing, but chip area consumption increases
Solution Approach 1:
The patent extracts and eliminates the separate data setup logic block from the systolic array architecture. Instead of having a dedicated component for reorganizing data, the patent integrates the data organization functionality directly into the processing elements themselves, which can reorganize and position data locally as needed for convolution computations, thereby reducing chip area.
Solution Approach 2:
The data setup and processing functions are merged into the processing elements. Each processing element is capable of both organizing its local data and performing computations, eliminating the need for a separate data setup logic block and reducing overall chip area while maintaining proper data organization for processing.
4Ease of operation
If a data setup logic block is used to reorganize data in systolic arrays, then data inputs are in proper order for processing, but energy consumption increases
Solution Approach 1:
The patent removes the separate data setup logic block that would consume energy during data reorganization. Instead, data organization is performed locally by processing elements using their integrated storage and control logic, which consumes significantly less energy than a dedicated data setup block would require.
Solution Approach 2:
Data is organized and positioned in the local storage of processing elements in advance before computation begins. This preliminary organization eliminates the need for continuous energy-consuming data reorganization operations during processing, as data is already in the proper order for convolution computations.
Data Source
AI summary
Disclosed is a processing unit for computing a convolution of an activations matrix (e.g., a N×N activations matrix) and a weights kernel (e.g., a M×M weights kernel). The processing unit specifically employs an array of processing elements and a hardware-implemented spiral algorithm to compute the convolution. Due to this spiral algorithm, the need for a discrete data setup logic block is avoided, activation values from the activations matrix can be pre-loaded into processing elements only one time so that the need to repeatedly access the activations matrix is avoided, and the computation can be completed in a relatively low number of clock cycles, which is independent of the number of activation values in the activation matrix and which is equal to the number of weight values in a weights kernel. Also disclosed is an associated processing method.