Processor 1-Wire Communication via GPIO Interrupts
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Solution Overview
Problem
When an electronic device interlocks with an accessory device, the use of a micro controller unit (MCU) for 1-wire communication leads to increased power consumption and component costs, and existing methods like GPIO bit banging can result in timing errors and degraded system performance.
Innovation Solution
Implementing a 1-wire communication method without adding a separate chip like an FPGA or MCU, by allocating independent clock channels for data interfaces and using processor resources to manage input/output operations, thereby reducing power consumption and maintaining system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an MCU chip is used for 1-wire communication, then communication functionality is achieved, but power consumption increases and component cost increases
Solution Approach 1:
The patent extracts the MCU chip from the system and replaces it with processor resources. The processor directly handles 1-wire communication through its existing GPIO pins and interrupt mechanisms, eliminating the need for a separate MCU chip and its associated power consumption.
Solution Approach 2:
The patent makes the processor multi-functional by using its existing GPIO pins and interrupt handling capabilities to perform 1-wire communication tasks. The processor's existing resources are leveraged to serve multiple purposes: general computing, 1-wire communication, and device management, thereby eliminating the need for dedicated communication hardware.
2Adaptability or versatility
If an MCU chip is used for 1-wire communication, then communication functionality is achieved, but component cost increases
Solution Approach 1:
The patent removes the MCU chip from the component list and replaces it with processor resources. This extraction reduces component count and assembly complexity while maintaining full 1-wire communication functionality through the processor's existing interfaces.
Solution Approach 2:
The patent merges the 1-wire communication functionality with the processor's existing GPIO and interrupt systems. By combining these functions into a single integrated approach, the system eliminates the need for separate communication hardware and reduces overall system complexity.
3Device complexity
If GPIO bit banging method is used, then no separate chip is needed, but timing errors occur and system performance degrades
Solution Approach 1:
The patent implements feedback mechanisms through interrupt-driven communication. The processor continuously monitors the 1-wire bus through interrupt signals, allowing real-time detection and response to communication events. This feedback loop ensures accurate timing and data transmission without the manual bit-banging approach.
Solution Approach 2:
The patent replaces the mechanical manual bit-banging process with an automated interrupt-driven communication system. Instead of manually controlling GPIO pins in a loop, the system uses hardware interrupts to automatically trigger processor actions, eliminating timing errors associated with manual control.
4Reliability
If processor resources are locked for communication, then communication stability is improved, but other processes cannot execute and system performance degrades
Solution Approach 1:
The patent implements dynamic resource management where the processor can switch between communication tasks and other processes based on interrupt signals. Instead of locking resources, the system dynamically allocates processor attention to communication events only when needed, allowing other processes to execute during idle periods.
Solution Approach 2:
The patent uses periodic interrupt-driven communication instead of continuous locked processing. The processor periodically checks for communication events through interrupt signals, allowing other processes to execute between communication cycles. This periodic approach maintains communication stability while preserving system productivity.
Data Source
AI summary
An electronic device is provided. The electronic device includes a display, a first data interface circuit including a port for connecting with an external device, and configured to exchange serial data with the external device, at least one processor operatively connected with the first data interface circuit, and a memory operatively connected with the at least one processor, the memory stores instructions that cause the at least one processor to allocate a plurality of input/output ports for processing serial data received from the first data interface circuit in parallel, and receive a first signal from the external device through the first data interface circuit, in response to the first signal being received, identify a port set to be in an active state among the plurality of input/output ports, identify the first signal by using the port that is identified as being in the active state, and display information.