Processor-Accelerator Coherent Messaging Without Cache Line Pulls
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Solution Overview
Problem
Existing frameworks for communication between a processor core and an accelerator, such as AI processing units, suffer from inefficiencies including cache pollution, high latency, and increased bandwidth usage, which hinder scalable and efficient computing systems.
Innovation Solution
Implementing a system that enables coherent communication between a processor core and an accelerator through a dedicated signaling bus and in-place updates of cache lines using non-cached stores, allowing the accelerator to install messages directly into a cache accessible to the processor core without pulling cache lines across chips, thus preventing cache pollution and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the accelerator pulls cache lines across chips to communicate with the processor core, then communication coherence is achieved, but cache pollution increases and bandwidth consumption rises
Solution Approach 1:
The patent extracts the communication mechanism from traditional cache line pulling and implements a dedicated signaling bus for status updates. The accelerator uses a separate communication channel to send status messages to the processor core without interfering with the cache coherence protocol, thereby eliminating cache pollution while maintaining communication reliability
Solution Approach 2:
The patent introduces a signaling bus as an intermediary communication channel between the accelerator and processor core. This dedicated bus serves as a mediator that allows status updates to be transmitted without using the cache infrastructure, preventing bandwidth consumption and cache pollution while ensuring coherent communication
2Reliability
If the accelerator pulls cache lines across chips to communicate with the processor core, then communication coherence is achieved, but latency increases
Solution Approach 1:
The patent extracts the status communication function from the cache line pulling mechanism. By using a dedicated signaling bus for status updates, the system eliminates the time-consuming cache line transfer operations across chips, thereby reducing communication latency while maintaining coherence through the separate signaling channel
Solution Approach 2:
The patent segments the communication channel into two independent paths: one for data transfer through the cache system and another for status communication through the signaling bus. This segmentation allows status updates to occur independently without being constrained by cache line transfer timing, reducing overall communication latency
3Adaptability or versatility
If traditional communication frameworks are used between processor core and accelerator, then system compatibility is maintained, but cache pollution occurs
Solution Approach 1:
The patent introduces a signaling bus as an intermediary that enables the accelerator to communicate status information without using the cache system. This intermediary channel maintains system compatibility by working alongside existing cache protocols while preventing cache pollution through separate communication paths
Solution Approach 2:
The patent segments communication into data paths (using existing cache infrastructure for compatibility) and status paths (using dedicated signaling bus). This segmentation allows the system to maintain compatibility with traditional frameworks while eliminating cache pollution through the separate status communication channel
Data Source
AI summary
One or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to communication between a processor core and an accelerator. For example, a system can comprise a memory that can store computer executable components. The system can further comprise a processor that can execute the computer executable components stored in the memory, wherein the computer executable components can comprise a tracking component that can track a running state of an accelerator during execution of one or more functions by the accelerator. The computer executable components can further comprise an installation component that can install, via the accelerator, a message in a cache accessible to a processor core, wherein a cache line comprised within the cache can be updated based on installation of the message in the cache.