Processor Accelerator Large Memory Transaction Stores
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing microprocessor chip devices face performance limitations due to round-trip latency in wide atomic stores to coprocessors, which can cause processors to idle or stall, preventing parallel work.
Innovation Solution
A processor accelerator is employed to perform large memory transaction (LMT) stores to coprocessors, offloading wide atomic stores from the processor and mitigating round-trip latency through iterative LMTLINE-by-LMTLINE storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor performs wide atomic stores to coprocessors, then data integrity is ensured through atomic operations, but round-trip latency causes the processor to idle or stall
Solution Approach 1:
A processor accelerator is introduced as an intermediary component between the processor and coprocessor. The accelerator handles wide atomic store operations to the coprocessor, allowing the processor to issue store instructions and continue execution without waiting for the slow coprocessor response. The accelerator manages the actual data transfer and synchronization, eliminating the stall from the critical processor path while maintaining atomicity guarantees.
Solution Approach 2:
The wide atomic store operation is segmented into multiple LMTLINE-by-LMTLINE transfers. Instead of performing one large atomic store that blocks the processor, the operation is divided into smaller line-sized transfers that can be processed iteratively by the accelerator. This segmentation allows the processor to initiate the operation and continue work while the accelerator completes the transfers in the background.
2Reliability
If the processor waits for wide atomic store completion, then atomicity is maintained, but parallel work execution is prevented
Solution Approach 1:
The processor accelerator serves as a mediator that assumes responsibility for maintaining atomicity during wide store operations. The processor issues store instructions to the accelerator and can immediately proceed with other work. The accelerator ensures atomicity by managing the iterative LMTLINE transfers and coordinating with the coprocessor, thereby decoupling the atomicity guarantee from the processor's execution flow and enabling parallel work execution.
Solution Approach 2:
The processor performs preliminary actions by issuing the wide store instruction to the accelerator and then immediately transitions to executing other work. The actual data transfer and atomicity enforcement are performed as preliminary background operations by the accelerator without blocking the processor. This allows the processor to maintain productivity through parallel work execution while the accelerator ensures atomicity is preserved.
3Quantity of substance
If LMT stores are performed iteratively LMTLINE-by-LMTLINE, then large data sets can be transferred, but the operation appears complex from the processor's perspective
Solution Approach 1:
The processor accelerator abstracts the complexity of iterative LMTLINE-by-LMTLINE transfers from the processor. The processor simply issues a single wide store instruction with the data set parameters, and the accelerator handles all the complexity of breaking down the operation into line-sized transfers, managing the iterative process, and coordinating with the coprocessor. This intermediary approach allows large data sets to be transferred while maintaining simplicity at the processor level.
Solution Approach 2:
The processor accelerator performs self-service by automatically managing the iterative LMTLINE transfer process without requiring processor intervention. Once the processor initiates the wide store operation, the accelerator independently handles the decomposition into line transfers, the iterative transmission to the coprocessor, and the reassembly of results. This self-service capability allows large data set transfers while presenting a simple single-instruction interface to the processor.
Data Source
AI summary
A system and corresponding method perform large memory transaction (LMT) stores. The system comprises a processor associated with a data-processing width and a processor accelerator. The processor accelerator performs a LMT store of a data set to a coprocessor in response to an instruction from the processor targeting the coprocessor. The data set corresponds to the instruction. The LMT store includes storing data from the data set, atomically, to the coprocessor based on a LMT line (LMTLINE). The LMTLINE is wider than the data-processing width. The processor accelerator sends, to the processor, a response to the instruction. The response is based on completion of the LMT store of the data set in its entirety. The processor accelerator enables the processor to perform useful work in parallel with the LMT store, thereby improving processing performance of the processor.