Processor Accelerator Core Load Balancing
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Solution Overview
Problem
Existing infrastructure struggles to maintain high-speed transmission of encrypted data due to computational loads on CPUs and overutilization of accelerator devices, leading to slowed throughput and resource inefficiencies.
Innovation Solution
Offloading cryptographic and compression tasks from the CPU to accelerator devices, with a resource manager that selects accelerator cores based on utilization and priority, and implements load balancing and coherent memory management to prevent bottlenecks and memory conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cryptographic operations are performed on the CPU to protect data, then data security is improved, but computational load increases causing delays and reduced throughput
Solution Approach 1:
The patent extracts cryptographic operations from the CPU and relocates them to dedicated accelerator devices. The CPU offloads encryption and decryption tasks to these specialized hardware components, which are designed specifically for cryptographic processing. This separation allows the CPU to focus on general-purpose computing while accelerators handle security-critical operations, resolving the contradiction between maintaining data security and preserving system throughput.
Solution Approach 2:
The patent introduces accelerator devices as intermediary components between the CPU and data transmission pathways. These accelerators act as mediators that perform cryptographic operations on data packets, reducing the computational burden on the CPU. The accelerators receive data from the CPU, perform encryption/decryption, and return processed data, thereby maintaining security while preventing throughput degradation.
2Power
If multiple accelerator devices are used to offload tasks, then computational capacity is improved, but overutilization of specific accelerators slows throughput
Solution Approach 1:
The patent implements dynamic workload distribution across multiple accelerator devices. The system continuously monitors the utilization status of each accelerator and dynamically assigns new cryptographic tasks to the least busy accelerators. This dynamic load balancing prevents any single accelerator from becoming a bottleneck, ensuring that the increased computational capacity translates into maintained or improved throughput rather than creating new bottlenecks.
Solution Approach 2:
The patent employs feedback mechanisms where the system monitors accelerator utilization metrics and uses this information to make real-time decisions about task assignment. When an accelerator becomes overutilized, the system receives feedback about its status and redirects subsequent tasks to underutilized accelerators. This closed-loop control ensures optimal distribution of work across the accelerator fleet, preventing throughput degradation despite high computational demands.
3Use of energy by moving object
If cryptographic operations are offloaded to accelerator devices, then CPU computational load is reduced, but resource management complexity increases
Solution Approach 1:
The patent designs accelerator devices with universal interfaces and standardized communication protocols that allow them to work with multiple different CPU architectures and operating systems. The resource management system implements a unified interface layer that abstracts the complexity of managing multiple accelerators, presenting a consistent API to applications regardless of the underlying hardware configuration. This universality reduces resource management complexity while maintaining the benefit of CPU load reduction.
Data Source
AI summary
Examples described herein relate to a processor that includes a general purpose processor core and an accelerator core and a plurality of distributed accelerator cores coupled to the processor. In some examples, the processor is to select an accelerator core from among the accelerator core and the plurality of distributed accelerator cores to perform at least one operation based on accelerator core utilization. In some examples, the accelerator core and the plurality of distributed accelerator cores perform encryption, decryption, compression, and/or decompression operations.