Processor-Accelerator Coherent Signaling Bus for Low-Latency Sync

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Solution Overview

Problem

Existing frameworks for communication between a processor core and an accelerator, such as AI processing units, suffer from inefficiencies including cache pollution, high latency, and bandwidth consumption, making it difficult to scale computing systems effectively.

Innovation Solution

A system utilizing a dedicated signaling bus and non-cached stores for coherent communication between a processor core and an accelerator, enabling in-place updates of cache lines without pulling cache lines across chips, thereby preventing cache pollution and reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing communication frameworks are used between processor core and accelerator, then communication can be established, but cache pollution occurs and bandwidth is consumed

Engineering Contradiction:

Improvecommunication coherenceVSAvoidbandwidth consumption

Core Design Contradiction:

ReliabilityVSLoss of substance

Solution Approach 1:

The communication path is segmented into separate signaling and data pathways. The signaling bus carries only control signals and addresses, while data remains in local caches, preventing unnecessary cache line transfers and bandwidth consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A dedicated signaling bus acts as an intermediary between the processor core and accelerator, enabling communication of control signals and addresses without requiring data movement through cache structures, thus avoiding cache pollution.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If cache lines are pulled across chips for communication, then data access is enabled, but latency increases

Engineering Contradiction:

Improvedata synchronizationVSAvoidcommunication latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The control signaling function is extracted from the data path. By using a separate signaling bus for control communication, the system enables synchronization without extracting and transferring cache lines across chips, reducing latency.

Inventive Principle:

Principle #2Taking out (Extraction)

3Productivity

If dedicated signaling infrastructure is added, then communication efficiency improves, but device complexity increases

Engineering Contradiction:

Improvecommunication efficiencyVSAvoidbus architecture

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The signaling bus serves multiple functions including address transmission, control signaling, and status communication between processor core and accelerator, reducing the need for separate dedicated structures for each function.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12632385B2Coherent communication between a processor core and an accelerator

Publication Date: 2026.05.19 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

One or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to communication between a processor core and an accelerator. For example, a system can comprise a memory that can store computer executable components. The system can further comprise a processor that can execute the computer executable components stored in the memory, wherein the computer executable components can comprise a tracking component that can track a running state of an accelerator during execution of one or more functions by the accelerator. The computer executable components can further comprise an installation component that can install, via the accelerator, a message in a cache accessible to a processor core, wherein a cache line comprised within the cache can be updated based on installation of the message in the cache.