Processor Hardware Accumulator Reset for Zero-Overhead Loops
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Solution Overview
Problem
Current processor architectures, particularly VLIW machines, face significant calculational overhead when resetting accumulators during image processing, which breaks pipelined execution and hampers the efficiency of zero-overhead loops in driver assistance systems and other image processing applications.
Innovation Solution
The method involves using a hardware circuit to generate and manage reset signals for accumulators within a processor, allowing for zero-overhead loop execution by logically ANDing and ORing event outputs to avoid breaking pipelined execution, with an address generation unit calculating memory addresses for image patches and resetting the accumulator responsive to specific events while maintaining pipelined processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional software-based accumulator reset is used, then implementation simplicity is maintained, but pipelined execution is broken and calculational overhead increases
Solution Approach 1:
The patent replaces the software-based accumulator reset mechanism with a hardware circuit that automatically generates reset signals. This substitution eliminates the need for software intervention in the reset process, thereby maintaining pipelined execution continuity and reducing calculational overhead while introducing dedicated hardware logic for the reset function.
Solution Approach 2:
The patent introduces an intermediary hardware circuit that sits between the accumulator and the control logic. This intermediary circuit receives event signals and automatically generates appropriate reset signals without breaking the pipelined execution flow, effectively mediating between the need for reset functionality and the requirement to maintain pipeline efficiency.
2Productivity
If accumulator reset breaks pipelined execution, then reset functionality is achieved, but processing efficiency decreases
Solution Approach 1:
The patent implements preliminary action by pre-configuring the hardware circuit to generate reset signals in advance based on event conditions. The reset mechanism is prepared beforehand and automatically activates when the appropriate event occurs, eliminating the need to pause pipelined execution for reset operations and thus maintaining processing efficiency.
Solution Approach 2:
The patent ensures continuity of useful action by designing the hardware circuit to generate reset signals that do not interrupt the pipelined execution flow. The reset function is integrated into the continuous operation of the pipeline, allowing accumulators to be reset without stopping the processing stream, thereby maintaining continuous productive action.
3Productivity
If zero-overhead loops are implemented, then image processing efficiency is improved, but accumulator reset becomes problematic
Solution Approach 1:
The patent applies self-service by enabling the hardware circuit to automatically manage accumulator resets based on event conditions without requiring external software control. The circuit monitors events and autonomously generates reset signals, making the reset operation as transparent and automatic as the zero-overhead loop execution itself, thus resolving the conflict between loop efficiency and reset operability.
Data Source
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Figure 3
Figure 4a~4b
AI summary
A processor is provided with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the selected event. Responsive to the reset signal, the accumulator is reset to zero or another initial value while avoiding breaking pipelined execution of the processor.