Processor Address Buffer Management via Assembler Pre-calculation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional processor designs for address buffer management require complex logical circuits with two adders in series and a two-grade MUX, leading to increased hardware costs and reduced frequency and time sequence efficiency.
Innovation Solution
Implementing address buffer management by shifting arithmetic logic from the processor to an assembler, where intermediate values are calculated and encapsulated into instructions, allowing the processor to perform core operations for automatic-increment or automatic-decrement operations, thereby simplifying the logical circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If arithmetic logic for address buffer management is implemented in the processor using two adders in series and a two-grade MUX, then address buffer management can be achieved, but hardware costs increase and processor frequency decreases
Solution Approach 1:
The patent extracts the arithmetic logic operations from the processor and implements them in the assembler instead. The assembler calculates intermediate values (aa_wrap and aa_test) during instruction encoding, and the processor only needs to perform simple comparisons and selections based on these pre-calculated values, thereby removing the complex adder and MUX circuitry from the processor.
Solution Approach 2:
The patent performs the complex arithmetic calculations in advance during the instruction encoding phase in the assembler. The intermediate values aa_wrap and aa_test are pre-calculated and embedded in the instruction, so when the processor executes the instruction, it only needs to perform simple operations based on these pre-prepared values, eliminating the need for complex runtime arithmetic circuits.
2Reliability
If two adders in series and a two-grade MUX are used for address buffer management, then address wrapping and testing can be performed, but hardware costs increase
Solution Approach 1:
The patent extracts the arithmetic logic operations from the processor and implements them in the assembler instead. The assembler calculates intermediate values (aa_wrap and aa_test) during instruction encoding, and the processor only needs to perform simple comparisons and selections based on these pre-calculated values, thereby removing the complex adder and MUX circuitry from the processor.
Solution Approach 2:
The patent replaces the mechanical hardware circuit implementation (adders and MUXes in the processor) with a software-based solution in the assembler. The complex arithmetic operations are performed as software instructions during encoding, and the results are stored in the instruction stream, eliminating the need for corresponding hardware circuits.
3Adaptability or versatility
If complex logical circuits are used for address buffer management, then address automatic-increment and automatic-decrement operations can be implemented, but processor frequency is reduced
Solution Approach 1:
The patent performs the complex arithmetic calculations in advance during the instruction encoding phase in the assembler. The intermediate values aa_wrap and aa_test are pre-calculated and embedded in the instruction, so when the processor executes the instruction, it only needs to perform simple operations based on these pre-prepared values, eliminating the need for complex runtime arithmetic circuits.
Solution Approach 2:
The patent divides the address buffer management functionality into two segments: complex arithmetic operations are performed in the assembler during encoding, while the processor only handles simple comparison and selection operations during execution. This segmentation allows each component to be optimized for its specific task, improving overall system speed.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The disclosure provides a device for implementing address buffer management of a processor, including: an assembler configured to perform operations to obtain intermediate values when the assembler encodes a set instruction for an address automatic-increment value and boundary values, and to encapsulate the intermediate values into the set instruction for the address automatic-increment value and boundary values; and a processor configured to determine, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation, so as to achieve the address buffer management. The disclosure also provides a method for implementing address buffer management of a processor, including: a processor decodes a set instruction for an address automatic-increment value and boundary values to obtain intermediate values, and determines, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation when the processor performs a load or store instruction, so as to realize the address buffer management. Through the device and the method of the disclosure, the hardware costs of the processor are reduced and design requirements of the processor's time sequence and energy efficiency are met.