Processor Address Generator for Fractional Step Updates
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Solution Overview
Problem
Current processor architectures face performance bottlenecks when updating memory addresses with fractional steps, as this requires additional software instructions, especially in kernel parts, leading to inefficiencies in data access and processing.
Innovation Solution
Incorporating an address generator within the processor that updates an offset value by a fractional step, allowing for efficient address generation by integrating functional units such as adders, quantizers, and modulo counters, enabling address generation directly in hardware and reducing computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If address updating is performed by software instructions in kernel parts, then address updates can be performed with flexibility, but system performance deteriorates due to additional executed instructions
Solution Approach 1:
The patent merges the address generation functionality into the processor core by integrating an address generator unit that includes an adder and a quantizer. This allows fractional address updates to be performed directly in hardware within the processor core, combining the flexibility of software-controlled fractional steps with the speed of hardware execution, thereby resolving the contradiction between adaptability and productivity
Solution Approach 2:
The patent introduces a quantizer as an intermediary component between the fractional step input and the address register update mechanism. The quantizer converts fractional step values into appropriate address increments, enabling flexible fractional address updates while maintaining efficient hardware-based execution that does not require additional software instructions in kernel parts
2Speed
If fractional address updates are performed by external hardware units, then address generation speed is improved, but flexibility deteriorates as addresses are not accessible by software instructions
Solution Approach 1:
The patent combines the address generator unit with the processor core, merging hardware-based fractional address generation with software-controlled instruction execution. The address generator is integrated into the data processing path within the processor core, allowing generated addresses to be directly accessible to software instructions while maintaining high-speed hardware-based generation
Solution Approach 2:
The address generator unit is designed with multi-functionality, serving both as a high-speed hardware address generation mechanism and as a software-accessible component. The unit can operate in different modes depending on whether it is controlled by software instructions or operating autonomously in kernel parts, providing universal functionality that satisfies both speed and flexibility requirements
Data Source
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AI summary
A processor (1a, 1b) for processing data is provided. The processor (1a, 1b) comprises an address generator (2, 100, 200), which is operative to generate an address (8) based on a base address and a fractional step (?).