Processor Address Translation Log Area for TLB Power Reduction
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Solution Overview
Problem
Current address translation mechanisms in CPUs face inefficiencies due to increased power consumption and circuit area requirements when handling access permission violations, particularly when storing real addresses for debugging purposes, which can lead to performance degradation and higher resource usage.
Innovation Solution
A processing device that includes a memory with a log area and a processor configured to perform address translations, determine access permission violations, and record virtual and real addresses in the log area upon retranslation, reducing the need for the translation lookaside buffer (TLB) to store real addresses and thereby minimizing power consumption and circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the TLB stores real addresses for access permission violation logging, then debugging capability is improved, but power consumption and circuit area increase
Solution Approach 1:
The patent extracts the real address storage function from the TLB and relocates it to a separate log area in memory. The TLB only caches virtual-to-physical address translation, while real addresses for violation logging are stored externally, reducing TLB circuit complexity and power consumption while maintaining debugging capabilities.
Solution Approach 2:
The patent introduces an intermediary log area that acts as a buffer between the address translation mechanism and the debugging system. This log area stores real addresses separately, allowing the TLB to function efficiently without the overhead of storing real addresses, thus resolving the contradiction between debugging capability and power consumption.
2Reliability
If the TLB stores real addresses for access permission violation logging, then debugging capability is improved, but circuit area increases
Solution Approach 1:
The patent extracts the real address storage function from the TLB and relocates it to a separate log area in memory. The TLB only caches virtual-to-physical address translation, while real addresses for violation logging are stored externally, reducing TLB circuit complexity and power consumption while maintaining debugging capabilities.
Solution Approach 2:
The patent moves real address storage from the two-dimensional TLB structure to a separate memory dimension (log area). This spatial separation allows the TLB to maintain its compact cache structure for fast address translation while real addresses are stored in a dedicated logging region, reducing overall circuit area requirements.
3Adaptability or versatility
If complex configuration settings are used to handle more virtual machines and processes, then system capacity is improved, but translation time increases
Solution Approach 1:
The patent performs address translation configuration setup in advance, storing translation parameters and access permission settings in a log area before violations occur. This preliminary preparation allows the address translation mechanism to quickly retrieve pre-configured settings during runtime, handling multiple virtual machines and processes without increasing translation time.
Solution Approach 2:
The patent uses template-based configuration copying where standard address translation settings are predefined and can be rapidly replicated for multiple virtual machines and processes. This eliminates the need to manually configure each translation rule, maintaining fast translation performance while supporting increased system capacity.
Data Source
AI summary
A processing device includes a processor configured to output a memory access instruction issued by a process executed on a virtual machine and a virtual address targeted by the memory access instruction. The processor is configured to perform first translation of translating the virtual address into a real address of a virtual memory. The processor is configured to perform second translation of translating the real address into a physical address of a physical memory. The processor is configured to determine, based on the memory access instruction and an access permission attribute of the real address, whether an access permission violation occurs. The processor is configured to perform, upon determining that an access permission violation occurs, retranslation of translating the virtual address into the real address. The processor is configured to record the virtual address and the real address obtained by the retranslation in a log area of a memory.