Processor Address Mapping to Persistent Storage
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Solution Overview
Problem
Current systems face performance issues due to the need for frequent data transfers between random access memory (RAM) and storage, as the address range of storage is broader than the memory address space of a processor, leading to increased latency and reduced performance.
Innovation Solution
A computer apparatus and method that maps an address range of a data block in persistent storage into an accessible memory address range of a processor, ensuring direct access and maintaining cache coherency across multiple memories to reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is frequently transferred between RAM and storage to ensure processor access, then data availability is improved, but access latency increases and performance deteriorates
Solution Approach 1:
The patent merges the storage address space with the processor memory address space through address mapping, allowing the processor to access storage devices directly as if they were memory. This integration eliminates the need for frequent data transfers between RAM and storage, reducing access latency while maintaining data availability.
Solution Approach 2:
The patent introduces an address mapping mechanism as an intermediary layer between the processor and storage device. This mapping layer translates processor memory addresses to storage device addresses, enabling direct access without requiring data to be physically moved between RAM and storage, thus reducing access time while preserving data availability.
2Quantity of substance
If the storage address range is broader than processor memory address space, then storage capacity is improved, but direct access by processor becomes difficult
Solution Approach 1:
The patent segments the broad storage address range into multiple addressable regions and maps these regions to the processor's memory address space. This segmentation allows the processor to access different portions of the storage device through its limited address space, effectively enabling direct access to large storage capacities.
Solution Approach 2:
The patent adds an address mapping dimension between the processor and storage device. Instead of directly mapping storage addresses to processor addresses, it introduces a mapping layer that translates between the two address spaces, allowing the processor to access storage devices with broader address ranges than the processor's native address space.
3Speed
If RAM caching strategies are used to minimize latency, then access speed is improved, but constant exchange between RAM and storage increases overhead
Solution Approach 1:
The patent extracts the need for intermediate RAM caching by enabling direct processor-to-storage access through address mapping. Data can be accessed directly from storage without being copied to and from RAM, eliminating the constant exchange overhead while maintaining fast access speeds through direct addressing.
Data Source
AI summary
A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors. In a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent.