Processor Allocation Circuit Port Binding
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Solution Overview
Problem
Current processor architectures face challenges in scalable port-binding and efficient allocation of micro-operations across execution pipelines, leading to performance degradation due to unbalanced workload distribution and inefficiencies in dynamic scheduling as the number of execution ports increases.
Innovation Solution
A single allocation scheme that utilizes port occupancy information, circular order allocation, and sliding to pre-bind micro-operations to specific execution ports, ensuring balanced workload distribution and improved pipeline usage, even with increasing allocation widths and asymmetric ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of execution ports is increased to improve processing capacity, then productivity increases, but device complexity increases and workload distribution becomes unbalanced
Solution Approach 1:
The patent segments the allocation of micro-operations to execution ports by dividing them into different types (first type and second type execution ports). The allocation circuit selectively allocates micro-operations based on their compatibility with specific port types, thereby managing complexity through structured segmentation while maintaining high processing capacity across multiple ports.
2Adaptability or versatility
If dynamic scheduling is used to improve flexibility in micro-operation allocation, then adaptability increases, but device complexity increases due to scheduling overhead
Solution Approach 1:
The patent applies preliminary action by pre-categorizing execution ports into different types before micro-operation allocation occurs. The allocation circuit uses these pre-established categories to make rapid allocation decisions, eliminating the need for complex real-time dynamic scheduling while maintaining adaptability through the pre-defined port type structure.
3Productivity
If circular order allocation with sliding is used to balance workload, then productivity improves through better pipeline usage, but device complexity increases due to allocation mechanism
Solution Approach 1:
The patent implements dynamics through the sliding mechanism in circular order allocation. The allocation circuit dynamically adjusts the starting position of micro-operation allocation in the circular order based on current port availability and workload conditions. This dynamic adjustment enables balanced workload distribution across execution ports while maintaining a relatively simple allocation circuit structure compared to full dynamic scheduling.
Data Source
AI summary
Systems, methods, and apparatuses relating to circuitry to implement scalable port-binding for asymmetric execution ports and allocation widths of a processor are described. In one embodiment, a hardware processor core includes a decoder circuit to decode instructions into sets of one or more micro-operations, an instruction decode queue to store the sets of one or more micro-operations, a plurality of different types of execution circuits that each comprise a respective input port and a respective input queue, and an allocation circuit comprising a plurality of allocation lanes coupled to the instruction decode queue and to the input ports of the plurality of different types of execution circuits, wherein the allocation circuit is to, for an input of micro-operations on the plurality of allocation lanes, generate a sorted list of occupancy of the input queues of each input port, generate a pre-binding mapping of the input ports of the plurality of different types of execution circuits to the plurality of allocation lanes in a circular order according to the sorted list, when a type of micro-operation from an allocation lane does not match a type of execution circuit of an input port in the pre-binding mapping, slide the pre-binding mapping so that the input port maps to a next allocation lane having a matching type of micro-operation to generate a final mapping of the input ports of the plurality of different types of execution circuits to the plurality of allocation lanes, and bind the input ports of the plurality of different types of execution circuits to the plurality of allocation lanes according to the final mapping.