Processor Approximate Computing Error Tracking
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Solution Overview
Problem
Current technologies have not effectively translated approximate computing concepts into commercially viable processor solutions, lacking practical implementations for reducing power consumption while allowing for reduced accuracy in computations.
Innovation Solution
A processor architecture that includes approximating functional units, an instruction cache, an instruction translator, architectural registers, an approximation control register, and snapshot storage, enabling computations to be performed with less than full accuracy while managing error accumulation and switching to full accuracy when error bounds are exceeded.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If approximate computing is implemented to reduce power consumption, then energy efficiency is improved, but computational accuracy deteriorates
Solution Approach 1:
The processor dynamically switches between approximate and exact computation modes based on runtime conditions. The approximation control register and error tracking mechanisms enable the system to adaptively select computation precision, transitioning from static to dynamic operation to optimize both power consumption and accuracy based on specific computational needs.
Solution Approach 2:
The invention changes the precision parameter of computational operations by introducing approximation modes with configurable error bounds. By modifying the computation parameter from full precision to approximate precision (controlled via approximation control registers and error tracking), the system achieves reduced power consumption while maintaining acceptable accuracy levels for specific applications.
2Use of energy by stationary object
If approximate computations are performed with reduced accuracy, then power consumption is reduced, but error accumulation increases
Solution Approach 1:
The system implements feedback mechanisms through error tracking registers that monitor accumulated errors during approximate computations. When error bounds are exceeded, the feedback triggers a switch to exact computation modes, creating a closed-loop control system that manages error accumulation while maintaining power efficiency.
Solution Approach 2:
The invention prepares for potential error accumulation by establishing error bounds and tolerance thresholds in advance. Snapshot storage mechanisms capture intermediate results that can be restored if error accumulation becomes problematic, providing a safety buffer before errors critically impact computation reliability.
3Measurement precision
If full accuracy computation is always performed, then computational precision is maintained, but power consumption increases
Solution Approach 1:
The computation process is segmented into approximate and exact portions based on error tracking. Rather than uniformly applying full precision to all operations, the system divides computations into segments where approximate computation is used for operations with acceptable error margins, and exact computation is applied only when necessary to maintain overall accuracy requirements.
Solution Approach 2:
The system applies partial action by performing computations at reduced precision (approximate mode) rather than full precision for all operations. This partial computation approach is sufficient for many applications where absolute maximum precision is not required, thereby reducing power consumption while meeting functional requirements.
4Use of energy by moving object
If approximate computing modes are introduced, then power efficiency is improved, but device complexity increases
Solution Approach 1:
The approximate functional units are designed to perform multiple functions: they can execute both approximate and exact computations, serve as regular functional units when not in approximation mode, and provide error tracking capabilities. This multi-functionality reduces the need for separate dedicated hardware for approximate computing, thereby limiting the increase in device complexity.
Solution Approach 2:
The invention merges approximate computing functionality with existing processor architecture by integrating approximation control registers, error tracking mechanisms, and snapshot storage into the conventional processor structure. This consolidation combines multiple functions into unified components rather than adding entirely separate systems, thus managing device complexity.
Data Source
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AI summary
A processor includes a decoder that decodes an instruction that instructs the processor to perform subsequent computations in an approximate manner and a functional unit that performs the subsequent computations in the approximate manner in response to the instruction. An instruction instructs the processor to clear an error amount associated with a value stored in a general purpose register of the processor. The error amount indicates an amount of error associated with a result of a computation performed by the processor in an approximate manner. The processor also clears the error amount in response to the instruction. Another instruction specifies a computation to be performed and includes a prefix that indicates the processor is to perform the computation in an approximate manner. The functional unit performs the computation specified by the instruction in the approximate manner specified by the prefix.