Processor Arbiter for DRAM Bank Conflict Scheduling
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Solution Overview
Problem
Current processors do not provide DRAM-aware protocol scheduling for read/write commands, leading to increased burden on the DRAM controller, lower data access efficiency, and longer response times.
Innovation Solution
A processor with storage modules and an arbiter that arranges and sequences read/write commands to prevent bank conflicts by prioritizing commands for different bank addresses, using a multi-stage arbiter circuit to optimize the transmission of commands to the memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the processor sends read/write commands to the DRAM controller without DRAM-aware protocol scheduling, then the processor implementation is simpler, but the burden on the DRAM controller increases and data access efficiency decreases
Solution Approach 1:
The patent introduces an arbiter as an intermediary component between the processor and DRAM controller. The arbiter receives read/write commands from multiple storage modules, schedules them according to DRAM bank addresses, and transmits them to the memory controller in an optimized sequence. This mediator handles the complex scheduling logic, keeping the processor implementation simple while improving data access efficiency by preventing bank conflicts.
Solution Approach 2:
The arbiter performs preliminary scheduling and sequencing of read/write commands before they are transmitted to the memory controller. By pre-organizing the command sequence based on DRAM bank addresses and anticipating potential bank conflicts, the system prepares optimized command streams in advance, reducing the burden on the DRAM controller and improving overall data access efficiency.
2Device complexity
If the processor sends read/write commands without protocol scheduling, then the processing logic is simpler, but the response time increases
Solution Approach 1:
The arbiter acts as a mediator that optimizes command sequencing to reduce response time. It receives commands from multiple storage modules, schedules them based on DRAM bank addresses to prevent bank conflicts, and transmits them to the memory controller in an optimized sequence, thereby reducing the time lost due to waiting and retransmissions.
Solution Approach 2:
The system performs preliminary scheduling and sequencing of read/write commands in the arbiter before transmission to the memory controller. By pre-organizing commands and anticipating bank conflicts, the system reduces response time without complicating the core processing logic in the processor.
3Ease of operation
If multiple storage modules send read/write commands simultaneously without scheduling, then the storage modules operate independently and simply, but the DRAM controller burden increases
Solution Approach 1:
The arbiter serves as an intermediary that receives commands from multiple independently operating storage modules. Each storage module continues to operate simply without complex scheduling logic, while the arbiter centralizes the scheduling function, organizing commands according to DRAM bank addresses and reducing the burden on the DRAM controller.
Solution Approach 2:
The patent extracts the complex scheduling and sequencing logic from the storage modules and DRAM controller, placing it in the dedicated arbiter component. This allows storage modules to remain simple and independent while the arbiter handles the complex task of command sequencing to prevent bank conflicts and reduce controller burden.
Data Source
AI summary
A processor includes a plurality of storage modules and an arbiter, where the storage modules are arranged for storing a plurality of read/write commands, respectively, and the read/write commands are arranged to read/write a memory external to the processor; and the arbiter is coupled to the storage modules, and is arranged to receive the read/write commands from the storage modules, and arrange a sequence of the read/write commands for transmitting to a memory controller.