Processor Arithmetic Device Synchronization Control
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Solution Overview
Problem
Existing processors with different types of arithmetic devices struggle to synchronize their operations effectively, leading to suboptimal processing performance.
Innovation Solution
The processor is designed with a first arithmetic device that executes instructions and a second arithmetic device that synchronizes with the first device using synchronization information, allowing coordinated execution of processes across different types of arithmetic units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If different types of arithmetic devices execute instructions independently, then each device can operate autonomously, but processing performance deteriorates due to lack of coordination
Solution Approach 1:
The patent implements feedback through synchronization information that the first arithmetic device sends to the second arithmetic device. The second device waits for this feedback before executing dependent instructions, ensuring coordinated operation and improving processing performance through controlled inter-device communication.
Solution Approach 2:
The patent applies preliminary action by having the second arithmetic device wait for synchronization information from the first device before executing instructions that depend on the first device's results. This preliminary waiting period ensures that data is ready before use, preventing errors and improving overall efficiency.
2Reliability
If the second arithmetic device waits for synchronization information, then coordination between devices is improved, but execution time increases due to waiting
Solution Approach 1:
The patent ensures continuity of useful action by allowing the second arithmetic device to prepare for synchronization in advance and by ensuring that the first device sends synchronization information as soon as possible. This minimizes the waiting time while maintaining reliable coordination between devices.
Data Source
AI summary
A processor includes a first arithmetic device configured to execute a first instruction, and a second arithmetic device configured to execute a second instruction and a third instruction. The first arithmetic device calculates first data by executing the first instruction. The second arithmetic device stops execution of the third instruction based on the second instruction which is an instruction for waiting issuance of first synchronization information, and thereafter executes the third instruction that uses the first data, based on the issuance of the first synchronization information from the first arithmetic device.