Processor Assignable Register Set for Interrupt Latency
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Solution Overview
Problem
Existing interrupt controller systems in microprocessors and microcontrollers are inflexible and wasteful with memory resources, particularly when managing multiple interrupt sources, leading to high ISR latency and significant processor time consumption.
Innovation Solution
A processor with a central processing unit (CPU) and multiple CPU register sets, controlled by multiplexer logic and programmable configuration registers, allows switching between register sets based on programmable conditions such as interrupt priority or identification, optimizing register usage and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a separate shadow register set is provided for ISRs to reduce latency, then interrupt latency is reduced, but memory resources are wasted
Solution Approach 1:
The patent implements dynamic switching between the main register set and shadow register set based on interrupt conditions. The multiplexer logic automatically selects the appropriate register set when an interrupt occurs, and switches back after the interrupt service routine completes. This dynamic allocation allows the shadow register set to be used only when needed, reducing memory waste while maintaining low interrupt latency.
2Productivity
If a shadow register set is provided for every interrupt source, then interrupt handling is optimized, but device complexity increases
Solution Approach 1:
The patent creates a universal shadow register set that can serve multiple interrupt sources, rather than dedicating a separate shadow register set to each interrupt. The control logic identifies when any interrupt occurs and switches to the shadow register set accordingly. This multi-functional approach maintains efficient interrupt handling while significantly reducing the number of register sets needed compared to having one shadow set per interrupt source.
3Ease of operation
If high frequency interrupt requests are handled with high ISR latency, then processor time is consumed, but system simplicity is maintained
Solution Approach 1:
The patent prepares the shadow register set in advance as a ready-to-use alternative to the main register set. When an interrupt occurs, the system can immediately switch to the pre-configured shadow register set without delay. This preliminary preparation eliminates the need for time-consuming context saving and restoring operations during high-frequency interrupt handling, significantly improving processor time efficiency while maintaining system simplicity.
Data Source
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AI summary
A processor has a central processing unit (CPU), a first CPU register set, a second CPU register set, a multiplexer logic for either coupling the first or the second CPU register set with the CPU, and control logic for controlling the multiplexer logic to switch from the first CPU register set to the second CPU register set upon receipt of at least one of a plurality of interrupt signals, wherein the at least one of a plurality of interrupt signals must meet a condition that is programmable within the control logic.